Abstract is missing.
- Sensitivity-driven co-synthesis of distributed embedded systemsTi-Yen Yen, Wayne Wolf. 4-9 [doi]
- Multiple-process behavioral synthesis for mixed hardware-software systemsJay K. Adams, Donald E. Thomas. 10-15 [doi]
- An approach to interface synthesisJan Madsen, Bjarne Hald. 16-21 [doi]
- The Chinook hardware/software co-synthesis systemPai H. Chou, Ross B. Ortega, Gaetano Borriello. 22-27 [doi]
- Clustering for improved system-level functional partitioningFrank Vahid, Daniel D. Gajski. 28-35 [doi]
- Optimal code generation for embedded memory non-homogeneous register architecturesGuido Araujo, Sharad Malik. 36-41 [doi]
- Optimal register assignment to loops for embedded code generationDavid J. Kolson, Alexandru Nicolau, Nikil Dutt, Ken Kennedy. 42-47 [doi]
- Real-time multi-tasking in software synthesis for information processing systemsFilip Thoen, Marco Cornero, Gert Goossens, Hugo De Man. 48-53 [doi]
- Time-constrained code compaction for DSPsRainer Leupers, Peter Marwedel. 54-59 [doi]
- Industrial experience using rule-driven retargetable code generation for multimedia applicationsClifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya. 60-68 [doi]
- Real-time systems specification and verificationJoseph Sifakis. 69 [doi]
- Synthesis of pipelined DSP accelerators with dynamic schedulingPatrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man. 72-77 [doi]
- An exact methodology for scheduling in a 3D design spaceSamit Chaudhuri, Stephen A. Blythe, Robert A. Walker. 78-83 [doi]
- Procedure exlining: a transformation for improved system and behavioral synthesisFrank Vahid. 84-89 [doi]
- Array mapping in behavioral synthesisHerman Schmit, Donald E. Thomas. 90-95 [doi]
- On the use of VHDL-based behavioral synthesis for telecom ASIC designMark Genoe, Paul Vanoostende, Geert van Wauwe. 96-103 [doi]
- Scheduling and resource binding for low powerEnric Musoll, Jordi Cortadella. 104-109 [doi]
- Power analysis and low-power scheduling techniques for embedded DSP softwareMike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita. 110-115 [doi]
- A path-based technique for estimating hardware runtime in HW/SW-cosynthesisJörg Henkel, Rolf Ernst. 116-121 [doi]
- A comprehensive estimation technique for high-level synthesisSeong Yong Ohm, Fadi J. Kurdahi, Nikil Dutt, Min Xu. 122-127 [doi]
- Profiling in the ASP codesign environmentMatthew F. Parkinson, Sri Parameswaran. 128-133 [doi]
- WWW based structuring of codesignsPaul-Gerhard Plöger, Jörg Wilberg, Michel Langevin, Raul Camposano. 138-143 [doi]
- System level verification of video and image processing specificationsH. Samsom, Frank H. M. Franssen, Francky Catthoor, Hugo De Man. 144-149 [doi]
- Synthesis of system-level communication by an allocation-based approachJean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya. 150-155 [doi]
- Modeling and simulation of heterogeneous real-time systems based on a deterministic discrete event modelJürgen Teich, Lothar Thiele, Edward A. Lee. 156-161 [doi]
- A system level design methodology for the optimization of heterogeneous multiprocessorsMarkus Schwiegershausen, Peter Pirsch. 162-169 [doi]
- 1995 high level synthesis design repositoryPreeti Ranjan Panda, Nikil D. Dutt. 170-174 [doi]