Table of Contents

• A low cost CMOS polarimetric ophthalmoscope scheme for cerebral malaria diagnosticsXiaojin Zhao, Amine Bermak, Farid Boussaïd. 1-4 [doi]
• Multimodal proton and fluorescence image sensor for bio applicationsHirokazu Nakazawa, Makoto Ishida, Kazuaki Sawada. 5-9 [doi]
• Fabrication of a flexible neural interface device with CMOS-based smart electrodesToshihiko Noda, Takuya Kitao, Takasuke Ito, Kiyotaka Sasagawa, Takashi Tokuda, Yasuo Terasawa, Hiroyuki Tashiro, Hiroyuki Kanda, Takashi Fujikado, Jun Ohta. 10-14 [doi]
• Micro CMOS image sensor for multi-area imagingKiyotaka Sasagawa, Hiroyuki Masuda, Ayato Tagawa, Takuma Kobayashi, Toshihiko Noda, Takashi Tokuda, Jun Ohta. 15-18 [doi]
• A novel low-leakage 8T differential SRAM cellKhawar Sarfraz. 19-24 [doi]
• Area-efficient 3-input decimal adders using simplified carry and sum vectorsTso-Bing Juang, Hsin-Hao Peng, Chao-Tsung Kuo. 25-30 [doi]
• STT-RAM based energy-efficiency hybrid cache for CMPsJianhua Li, Chun Jason Xue, Yinlong Xu. 31-36 [doi]
• Embedded MRAM for high-speed computingWeisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli. 37-42 [doi]
• A high efficiency synchronous buck converter with adaptive dead time control for dynamic voltage scaling applicationsShaowei Zhen, Bo Zhang, Ping Luo, Kang Yang, Xiaohui Zhu, Jiangkun Li. 43-48 [doi]
• A low-power ultra-fast capacitor-less LDO with advanced dynamic push-pull techniquesXin-ming, Ze-kun Zhou, Bo Zhang. 54-59 [doi]
• Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theoremJamshaid Sarwar Malik, Jameel Nawaz Malik, Ahmed Hemani, N. D. Gohar. 60-65 [doi]
• Adaptive priority toggle asynchronous tree arbiter for AER-based image sensorAung Myat Thu Linn, Anh-Tuan Do, Shoushun Chen, Kiat Seng Yeo. 66-71 [doi]
• MUX-MCM based quantization VLSI architecture for H.264/AVC high profile encoderJiang Ying, Xinhua Chen, Yibo Fan, Xiaoyang Zeng. 72-77 [doi]
• Topology synthesis of analog circuits with yield optimization and evaluation using pareto frontsOliver Mitea, Markus Meissner, Lars Hedrich. 78-81 [doi]
• New 12-bit source-follower track-and-hold circuit suitable for high-speed applicationsMarcel Veloso Campos, André Luís Fortunato, Carlos Alberto dos Reis Filho. 82-85 [doi]
• A low-loss rectifier unit for inductive-powering of biomedical implantsQingyun Ma, Mohammad Rafiqul Haider, Yehia Massoud. 86-89 [doi]
• Prospects of 3D inductors on through silicon vias processes for 3D ICsYiorgos I. Bontzios, Michael G. Dimopoulos, Alkis A. Hatzopoulos. 90-93 [doi]
• Performance evaluation of air-gap-based coaxial RF TSV for 3D NoCLe Yu, Haigang Yang, Jia Zhang, Wei Wang. 94-97 [doi]
• Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-ICKai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon. 98-101 [doi]
• Worst case analysis for evaluating VLSI circuit performance bounds using an optimization methodSiwat Saibua, Liuxi Qian, Dian Zhou. 102-105 [doi]
• An easily testable routing architecture of FPGAMasahiro Iida, Kazuki Inoue, Motoki Amagasaki, Toshinori Sueyoshi. 106-109 [doi]
• Minimizing redundancy-based motion estimation design for high-definitionJeong-Hoon Kim, In Jung Lyu, Hyun June Lyu, Jun Rim Choi. 110-113 [doi]
• FPGA implementation of high sampling rate in-car non-stationary noise cancellation based on adaptive Wiener filterHong-Yuan Jheng, Yen-Hsiang Chen, Shanq-Jang Ruan, Ziming Qi. 114-117 [doi]
• MCM-based implementation of block FIR filters for high-speed and low-power applicationsPramod Kumar Meher, Yu Pan. 118-121 [doi]
• 1024-point pipeline FFT processor with pointer FIFOs based on FPGAGuanwen Zhong, Hongbin Zheng, ZhenHua Jin, Dihu Chen, Zhiyong Pang. 122-125 [doi]
• A 230mV 8-bit sub-threshold microprocessor for wireless sensor networkWei Jin, Sheng Lu, Weifeng He, Zhigang Mao. 126-129 [doi]
• Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cacheAsim Khan, Kyungsu Kang, Chong-Min Kyung. 130-135 [doi]
• Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applicationsAntonio Artés, José Luis Ayala, Ashoka Visweswara Sathanur, Jos Huisken, Francky Catthoor. 136-141 [doi]
• Improvements to satisfiability-based boolean function bi-decompositionHuan Chen 0001, João Marques-Silva. 142-147 [doi]
• A hybrid algorithm for the optimization of area and delay in linear DSP transformsLevent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro. 148-153 [doi]
• Early planning for RT-level delay insertion during clock skew-aware register bindingKeisuke Inoue, Mineo Kaneko. 154-159 [doi]
• Frequency-domain transient analysis of multitime partial differential equation systemsHaotian Liu, Fengrui Shi, Yuanzhe Wang, Ngai Wong. 160-163 [doi]
• Post-silicon failing-test generation through evolutionary computationErnesto Sánchez, Giovanni Squillero, Alberto Paolo Tonda. 164-167 [doi]
• Communication-aware middleware-based design-space exploration for Networked Embedded SystemsFranco Fummi, Davide Quaglia, Francesco Stefanni. 168-171 [doi]
• A general statistical estimation for application mapping in Network-on-ChipNaifeng Jing, Weifeng He, Zhigang Mao. 172-175 [doi]
• On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array systemJing Xie, Huimin Xing, Zhigang Mao. 176-179 [doi]
• Communication centric on-chip power grid models for networks-on-chipNizar Dahir, Terrence S. T. Mak, Alex Yakovlev. 180-183 [doi]
• A clock-less transceiver for global interconnectJian-Fei Jiang, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao. 184-187 [doi]
• An optimized TTA-like vertex shader datapath for embedded 3D graphics processing unitJizeng Wei, Yisong Chang, Wei Guo, Jizhou Sun. 188-191 [doi]
• A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resourcesZhiliang Qian, Ying Fei Teh, Chi-Ying Tsui. 192-195 [doi]
• Communication service for hardware tasks executed on dynamic and partial reconfigurable resourcesSurya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis. 196-199 [doi]
• Combinational logic synthesis for material implicationAnupam Chattopadhyay, Zoltan Endre Rakosi. 200-203 [doi]
• SNM-aware power reduction and reliability improvement in 45nm SRAMsSeokjoong Kim, Matthew R. Guthaus. 204-207 [doi]
• Self-dependent equivalent circuit modeling of electrostatic comb transducers for integrated MEMSToshiyuki Tsuchiya, Hiroyuki Tokusaki, Yoshikazu Hirai, Koji Sugano, Osamu Tabata. 208-213 [doi]
• Wide-band piezoresistive aero-acoustic microphoneZhijian Zhou, Man Wong, Libor Rufer. 214-219 [doi]
• Designs for improving the performance of an electro-thermal in-plane actuatorAlex Man Ho Kwan, Sichao Song, Xing Lu, Lei Lu, Ying Khai Teh, Ying Fei Teh, Eddie Wing Cheung Chong, Yan Gao, William Hau, Fan Zeng, Man Wong, Chunmei Huang, Akira Taniyama, Yoshihide Makino, So Nishino, Toshiyuki Tsuchiya, Osamu Tabata. 220-225 [doi]
• Uniform carbon nanotube diameter and nanoarray pitch for VLSI of 16nm P-channel MOSFETsYanan Sun, Volkan Kursun. 226-231 [doi]
• 3D NoC using through silicon Via: An asynchronous implementationPascal Vivet, Denis Dutoit, Yvain Thonnart, Fabien Clermidy. 232-237 [doi]
• ThruChip interface (TCI) for 3D networks on chipTadahiro Kuroda. 238-241 [doi]
• Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC)Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu. 242-247 [doi]
• Towards future VLSI interconnects using aligned carbon nanotubesYang Chai, Minghui Sun, Zhiyong Xiao, Yuan Li, Min Zhang, Philip C. H. Chan. 248-253 [doi]
• New SEC-DED-DAEC codes for multiple bit upsets mitigation in memoryMing Zhu, Li-yi Xiao, Hong Wei Luo. 254-259 [doi]
• Self-test method and recovery mechanism for high frequency TSV arrayJia Zhang, Le Yu, Haigang Yang, Y. L. Xie, F. B. Zhou, Wei Wang. 260-265 [doi]
• Fault tolerant design for low power hierarchical search motion estimation algorithmsCharvi Dhoot, Vincent John Mooney, Shubhajit Roy Chowdhury, Lap-Pui Chau. 266-271 [doi]
• On the functional test of Branch Prediction Units based on Branch History TableErnesto Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda. 278-283 [doi]
• Agent-based on-chip network using efficient selection methodMasoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 284-289 [doi]
• Network-on-Chip multicasting with low latency path setupWenmin Hu, Zhonghai Lu, Axel Jantsch, Hengzhu Liu, Botao Zhang, Dongpei Liu. 290-295 [doi]
• A fault-tolerant NoC using combined link sharing and partial fault link utilization schemeYing Fei Teh, Zhiliang Qian, Chi-Ying Tsui. 296-301 [doi]
• Two-levels of adaptive buffer for virtual channel router in NoCsCaroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Gianluca Palermo, Cristina Silvano. 302-307 [doi]
• System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logicAlberto Ghiribaldi, Daniele Ludovici, Michele Favalli, Davide Bertozzi. 308-313 [doi]
• Multirate hybrid continuous-time/discrete-time cascade 2-2 ΣΔ modulator for wideband telecomJ. Gerardo García-Sánchez, José Manuel de la Rosa Utrera. 314-318 [doi]
• A voltage mode power converter with the function of digitally duty cycle tuningXiaohui Zhu, Ping Luo, Shaowei Zhen, Kang Yang, Jiangkun Li, Zekun Zhou. 319-324 [doi]
• A high performance band-pass DAC architecture and design targeting a low voltage silicon processBrendan Mullane, Vincent O'Brien. 325-330 [doi]
• Clockless asynchronous delta modulator based ADC for smart dust applicationsVenkata Narasimha Manyam, Dhurv Chhetri, J. Jacob Wikner. 331-336 [doi]
• Low latency and energy efficient multicasting schemes for 3D NoC-based SoCsXiaohang Wang, Maurizio Palesi, Mei Yang, Yingtao Jiang, Michael C. Huang, Peng Liu 0016. 337-342 [doi]
• 3-D integration and the limits of silicon computationDinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch. 343-348 [doi]
• Architecture and design of a programmable 3D-integrated cellular processor array for image processingAlexey Lopich, Piotr Dudek. 349-353 [doi]
• Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming networkKai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon. 354-358 [doi]
• A battery-free energy harvesting system with the switch capacitor sampler (SCS) technique for high power factor in smart meter applicationsTzu-Chi Huang, Yao-Yi Yang, Yu-Huei Lee, Ming-Jhe Du, Shih-Hsien Cheng, Ke-Horng Chen. 359-362 [doi]
• A subthreshold digital maximum power point tracker for micropower piezoelectric energy harvesting applicationsJoseph Sankman, Dongsheng Ma. 363-367 [doi]
• Interface model based cyber-physical energy system design for smart gridJanet Meiling Wang Roveda, Susan Lysecky, Young Jun Son, Hyungtaek Chang, Anita Annamalai, Xiao Qin. 368-373 [doi]
• Design and analysis of on-chip charge pumps for micro-power energy harvesting applicationsWing-Hung Ki, Yan Lu, Feng Su, Chi-Ying Tsui. 374-379 [doi]
• SystemC AMS behavioral modeling of a CMOS video sensorFabio Cenni, Serge Scotti, Emmanuel Simeu. 380-385 [doi]
• Context-aware compiled simulation of out-of-order processor behavior based on atomic tracesRoman Plyaskin, Andreas Herkersdorf. 386-391 [doi]
• C-Routing: An adaptive hierarchical NoC routing methodologyManas Kumar Puthal, Virendra Singh, M. S. Gaur, Vijay Laxmi. 392-397 [doi]
• Positive realization of reduced RLCM netsJorge Fernandez Villena, L. Miguel Silveira. 398-403 [doi]
• 3D-IC floorplanning: Applying meta-optimization to improve performanceFelipe Frantz, Lioula Labrak, Ian O'Connor. 404-409 [doi]
• A more efficient arrangement of the sparse LU factorization for the large-scale circuit analysisJosef Dobes, David Cerny, Abhimanyu Yadav. 416-421 [doi]
• State space optimization within the DEVS model of computation for timing efficiencyH. Gregor Molter, André Seffrin, Sorin A. Huss. 422-427 [doi]
• High-throughput pipelined realization of adaptive FIR filter based on distributed arithmeticPramod Kumar Meher, Sang Yoon Park. 428-433 [doi]
• A full-mode FME VLSI architecture based on 8×8/4×4 adaptive Hadamard Transform for QFHD H.264/AVC encoderJialiang Liu, Xinhua Chen, Yibo Fan, Xiaoyang Zeng. 434-439 [doi]
• Robust design of sub-threshold flip-flop cells for wireless sensor networkWei Jin, Sheng Lu, Weifeng He, Zhigang Mao. 440-443 [doi]