Table of Contents

• VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplersDominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid. 1-6 [doi]
• Energy-efficient partitioning of hybrid caches in multi-core architectureDongwoo Lee, Kiyoung Choi. 1-6 [doi]
• Dynamic programming-based lifetime aware adaptive routing algorithm for Network-on-ChipLiang Wang, Xiaohang Wang, Terrence S. T. Mak. 1-6 [doi]
• Towards energy effective LDPC decoding by exploiting channel noise variabilityThomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana. 1-6 [doi]
• A common architecture for co-simulation of SystemC models in QEMU and OVP virtual platformsFilippo Cucchetto, Alessandro Lonardi, Graziano Pravadelli. 1-6 [doi]
• Implementation of power efficient multicore FFT datapaths by reordering the twiddle factorsSidinei Ghissoni, Eduardo A. C. da Costa, Angelo Goncalves da Luz. 1-6 [doi]
• Improved read and write margins using a novel 8T-SRAM cellFarshad Moradi, Jens Kargaard Madsen. 1-5 [doi]
• Laser-induced fault effects in security-dedicated circuitsRégis Leveugle, Paolo Maistri, Pierre Vanhauwaert, F. Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, G. Hubert, S. De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, C. Tavernier. 1-6 [doi]
• Soft error effects analysis and mitigation in VLIW safety-critical applicationsDavide Sabena, Matteo Sonza Reorda, Luca Sterpone. 1-6 [doi]
• Complementary logic interface for high performan optical computing with OLUTZhen Li, Sébastien Le Beux, Ian O'Connor, Christelle Monat, Xavier Letartre. 1-6 [doi]
• Self similarity and interval arithmetic based leakage optimization in RTL datapathsShilpa Pendyala, Srinivas Katkoori. 1-6 [doi]
• A quantum algorithm processor architecture based on register reorderingMasaki Nakanishi, Miki Matsuyama, Yumi Yokoo. 1-6 [doi]
• Low-power high-speed current mode logic using Tunnel-FETsWei-Yu Tsai, Huichu Liu, Xueqing Li, Vijaykrishnan Narayanan. 1-6 [doi]
• Multi-terminal PCB escape routing for digital microfluidic biochips using negotiated congestionJeffrey McDaniel, Daniel Grissom, Philip Brisk. 1-6 [doi]
• Through silicon via placement and mapping strategy for 3D mesh based Network-on-ChipKanchan Manna, Santanu Chattopadhyay, Indranil Sengupta. 1-6 [doi]
• Detailed placement accounting for technology constraintsAndrew A. Kennings, Nima Karimpour Darav, Laleh Behjat. 1-6 [doi]
• Inference of channel types in micro-architectural models of on-chip communication networksBernard van Gastel, Freek Verbeek, Julien Schmaltz. 1-6 [doi]
• Logic synthesis and verification on fixed topologyMasahiro Fujita, Alan Mishchenko. 1-6 [doi]
• A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flowZeineb Bel Hadj Amor, Laurence Pierre, Dominique Borrione. 1-6 [doi]
• Optimized active and power-down mode refresh control in 3D-DRAMsMatthias Jung 0001, Christian Weis, Norbert Wehn, MohammadSadegh Sadri, Luca Benini. 1-6 [doi]
• Simulated annealing-based placement for microfluidic large scale integration (mLSI) chipsJeffrey McDaniel, Brendon Parker, Philip Brisk. 1-6 [doi]
• Circuit to reduce Gate Induced Drain Leakage in CMOS output buffersHari Anand Ravi, Mayank Goel, Prasad Bhilawadi. 1-5 [doi]
• AES design space exploration new line for scan attack resiliencySk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri. 1-6 [doi]
• Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative studyGabriele Miorandi, Alberto Ghiribaldi, Steven M. Nowick, Davide Bertozzi. 1-6 [doi]
• Reducing test time for 3D-ICs by improved utilization of test elevatorsSreenivaas S. Muthyala, Nur A. Touba. 1-6 [doi]
• Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotationZoltán Endre Rákossy, Farhad Merchant, Axel Acosta Aponte, S. K. Nandy, Anupam Chattopadhyay. 1-6 [doi]
• Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessorK. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle. 1-6 [doi]
• Electromagnetic analysis and fault injection onto secure circuitsPaolo Maistri, Régis Leveugle, Lilian Bossuet, A. Aubert, Viktor Fischer, Bruno Robisson, Nicolas Moro, Philippe Maurine, Jean-Max Dutertre, Mathieu Lisart. 1-6 [doi]
• Decimal engine for energy-efficient multicore processorsAlberto Nannarelli. 1-6 [doi]
• Electromagnetic analysis, deciphering and reverse engineering of integrated circuits (E-MATA HARI)Laurent Chusseau, Rachid Omarouayache, Jeremy Raoult, Sylvie Jarrix, Philippe Maurine, Karim Tobich, Alexandre Boyer, Bertrand Vrignon, John Shepherd, Thanh-Ha Le, Maël Berthier, Lionel Rivière, Bruno Robisson, Anne-Lise Ribotta. 1-6 [doi]
• A low power 720p motion estimation processor with 3D stacked memoryShuping Zhang, Jinjia Zhou, Dajiang Zhou, Satoshi Goto. 1-6 [doi]
• Power dissipation effects on 28nm FPGA-based System on Chips neutron sensitivityG. Bruni, Paolo Rech, Lucas A. Tambara, Gabriel L. Nazar, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis, A. Paccagnell. 1-6 [doi]
• Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCsMatthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragan. 1-6 [doi]
• Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validationJesus-Andres Mendoza-Bonilla, Alejandro Cortez-Ibarra, Edgar-Andrei Vega-Ochoa, Francisco Rangel-Patino, Brandon Gore. 1-6 [doi]
• Reconfigurable forward homography estimation system for real-time applicationsVladan Popovic, Yusuf Leblebici. 1-6 [doi]
• Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variationHiroyuki Yamauchi, Worawit Somha. 1-6 [doi]
• A novel non-minimal turn model for highly adaptive routing in 2D NoCsManoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Masoud Daneshtalab, Mark Zwolinski. 1-6 [doi]
• Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusabilityMoon Gi Seok, Daejin Park, Geun Rae Cho, Tag Gon Kim. 1-6 [doi]
• Silicon photonics design rule checking: Application of a programmable modeling engine for non-Manhattan geometry verificationRuping Cao, John Ferguson, Fabien Gays, Youssef Drissi, Alexandre Arriordaz, Ian O'Connor. 1-6 [doi]
• Realizing a security aware triple modular redundancy scheme for robust integrated circuitsGunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian. 1-6 [doi]
• Automated functional coverage directed for complex digital systemsAlfonso Martinez Cruz, Ricardo Barrón Fernández, Herón Molina Lozano. 155-156 [doi]
• Study of on-chip vias of resonant rotary traveling wave oscillatorsJavier Osorio Figueroa, Monico Linares Aranda. 157-158 [doi]
• Modeling, analysis and exploration of layers: A 3D computing architectureZoltán Endre Rákossy. 159-160 [doi]
• Advances on the state of the art in QDI designMatheus T. Moreira, Ney Laert Vilar Calazans. 163-164 [doi]