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Viewing Publication 1 - 100 from 4365

2025

Dynamic Topology-Aware Flow Path Construction and Scheduling Optimization for Multilayered Continuous-Flow Microfluidic BiochipsMeng Lian 0001, Shucheng Yang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. aspdac 2025: 1364-1371 [doi]

Nature-GL: A Revolutionary Learning Paradigm Unleashing Nature's Power in Real-World Spatial-Temporal Graph LearningChuan Liu 0001, Chunshu Wu, Ruibing Song, Yousu Chen, Ang Li 0006, Michael C. Huang 0001, Tony Tong Geng. aspdac 2025: 865-871 [doi]

Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted DataJianfei Wang 0003, Jia Hou, Fahong Zhang 0002, Yishuo Meng, Yang Su 0003, Chen Yang 0005. aspdac 2025: 1302-1307 [doi]

Machine Learning-Based Real-Time Detection of Power Analysis Attacks Using Supply Voltage ComparisonsNan Wang 0003, Ruichao Liu, Yufeng Shan, Yu Zhu 0005, Song Chen 0001. aspdac 2025: 440-446 [doi]

High-Parallel In-Memory NTT Engine with Hierarchical Structure and Even-Odd Data MappingBing Li 0017, Huaijun Liu, Yibo Du, Ying Wang 0001. aspdac 2025: 86-92 [doi]

A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data RateYi Zhang 0092, Minzhe Tang, Zheng Li 0021, Dongfan Xu, Kazuaki Kunihiro, Hiroyuki Sakai 0009, Atsushi Shirane, Kenichi Okada 0001. aspdac 2025: 342-343 [doi]

MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMsManar Abdelatty, Jingxiao Ma, Sherief Reda. aspdac 2025: 995-1001 [doi]

2S: A Hybrid Ising-Classical-Machines Data-Driven QUBO Solver MethodArmin Abdollahi, Mehdi Kamal, Massoud Pedram. aspdac 2025: 914-920 [doi]

Towards Design Optimization of Analog Compute SystemsSara Achour. aspdac 2025: 857-864 [doi]

An Island Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided LogicUmar Afzaal, Seunggyu Lee, Youngsoo Shin. aspdac 2025: 476-482 [doi]

ChemComp: A Compilation Framework for Computing with Chemical Reaction NetworksNicolas Bohm Agostini, Connah Johnson, William Cannon, Antonino Tumeo. aspdac 2025: 872-878 [doi]

Graph-Based Timing Prediction at Early-Stage RTL Using Large Language ModelFahad Rahman Amik, Yousef Safari, Zhanguang Zhang, Boris Vaisband. aspdac 2025: 393-400 [doi]

DEMOTIC: A Differentiable Sampler for Multi-Level Digital CircuitsArash Ardakani, Minwoo Kang, Kevin He, Qijing Huang 0001, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek. aspdac 2025: 1328-1335 [doi]

Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing AwarenessYichen Cai, Linyu Zhu, Xinfei Guo. aspdac 2025: 1230-1236 [doi]

Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse KinematicsQiankai Cao, Yiqi Li, Juin Chuen Oh, Jie Gu 0001. aspdac 2025: 321-324 [doi]

AI-Guided Codesign for Novel Computing ParadigmsSuma George Cardwell, J. Darby Smith, Karan Patel, Andrew Maicke, Jared Arzate, Samuel Liu, Jaesuk Kwon, Christopher Allemang, Douglas Cale Crowder, Shashank Misra, Frances S. Chance, Catherine D. Schuman, Jean Anne C. Incorvia, James Bradley Aimone. aspdac 2025: 849-856 [doi]

ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDAHyunsu Chae, Song Hang Chai, Taiyun Chi, Sensen Li, David Z. Pan. aspdac 2025: 683-689 [doi]

A Practical Randomized GMRES Algorithm for Solving Linear Equation System in Circuit SimulationBaiyu Chen, Jiawen Cheng, Wenjian Yu. aspdac 2025: 183-189 [doi]

CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-ChipYan-Ting Chen, Zhidan Zheng, Shao-Yun Fang, Tsun-Ming Tseng, Ulf Schlichtmann. aspdac 2025: 1251-1256 [doi]

Zipper: Latency-Tolerant Optimizations for High-Performance BusesShibo Chen, Hailun Zhang, Todd M. Austin. aspdac 2025: 567-574 [doi]

Invited Paper: Boosting Standard Cell Library Characterization with Machine LearningZhengrui Chen, Chengjun Guo, Zixuan Song, GuoZhu Feng, Shizhang Wang, Li Zhang 0021, Xunzhao Yin, Zhenhua Wu, Zheyu Yan, Cheng Zhuo. aspdac 2025: 385-391 [doi]

Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot LearningHao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu. aspdac 2025: 93-99 [doi]

Leveraging Machine Learning Techniques for Traditional EDA Workflow EnhancementJinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, SeongHyeon Park, Jaemin Seo, Jongho Yoon, Seokhyeong Kang. aspdac 2025: 676-682 [doi]

PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog CircuitsYoungchang Choi, Sejin Park 0001, Ho-Jin Lee, Kyongsu Lee, Jae-Yoon Sim, Seokhyeong Kang. aspdac 2025: 842-848 [doi]

Paired-Spacing-Constrained Package Routing with Net Ordering OptimizationYi-Sian Ciou, Ying-Jie Jiang, Yi-Yu Liu, Shao-Yun Fang, Wen-Hao Liu 0001. aspdac 2025: 761-767 [doi]

Area-Oriented Optimization After Standard-Cell MappingAndrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli. aspdac 2025: 1112-1119 [doi]

Dual-branch cross-modal fusion with local-to-global learning for UAV object detectionBinyi Fang, Yixin Yang 0004, Jingjing Chang, Ziyang Gao, Hai-Bao Chen. aspdac 2025: 1126-1132 [doi]

Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator PerformanceArya Fayyazi, Mehdi Kamal, Massoud Pedram. aspdac 2025: 16-22 [doi]

Stochastic Multivariate Universal-Radix Finite-State Machine: a Theoretically and Practically Elegant Nonlinear Function ApproximatorXincheng Feng, Guodong Shen, JianHao Hu, Meng Li 0016, Ngai Wong. aspdac 2025: 211-217 [doi]

ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point MultiplierZhongyu Guan, Qiang Liu 0011, Guangdong Lin. aspdac 2025: 218-223 [doi]

Exploring and Exploiting Runtime Reconfigurable Floating Point Precision in Scientific Computing: a Case Study for Solving PDEsCong Hao. aspdac 2025: 1041-1047 [doi]

Pin Access-aware Multiple Via Pillar Co-Design for Routability OptimizationMan-Ling Hong, Ying-Jie Jiang, Shao-Yun Fang. aspdac 2025: 1237-1242 [doi]

An Edge AI and Adaptive Embedded System Design for Agricultural Robotics ApplicationsChun-Hsian Huang, Zhi-Rui Chen, Huai-Shu Hsu. aspdac 2025: 607-613 [doi]

Hardware Acceleration of Kolmogorov-Arnold Network (KAN) for Lightweight Edge InferenceWei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq Waqar, Tai-Hao Wen, Meng-Fan Chang, Shimeng Yu. aspdac 2025: 693-699 [doi]

DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable ArchitecturesHaojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin. aspdac 2025: 548-553 [doi]

Hardware Trojan Detection by Fine-grained Power Domain PartitioningTakahiro Ishikawa, Kose Yokooji, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani, Jun Shiomi. aspdac 2025: 1257-1263 [doi]

Cryo-Compact Modeling Based on Sparse Gaussian ProcessTetsuro Iwasaki, Takashi Sato 0001, Michihiro Shintani. aspdac 2025: 1426-1431 [doi]

A Hybrid Machine Learning and Numeric Optimization Approach to Analog Circuit DeobfuscationDipali Deepak Jain, Guangwei Zhao, Rajesh Kumar Datta, Kaveh Shamsi. aspdac 2025: 801-807 [doi]

Efficient Key Switching Accelerator for Fully Homomorphic EncryptionSeoyoon Jang, Sungjin Park, Dongsuk Jeon. aspdac 2025: 1288-1294 [doi]

WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth MemorySeoyoon Jang, Sangouk Jeon, Kwanghyun Shin, Dongkwon Lee, Hankyu Chi, Wookjin Shin, Changhyun Pyo, Jaeha Kim, Dongsuk Jeon. aspdac 2025: 945-951 [doi]

PPA-Aware Tier Partitioning for 3D IC Placement with ILP FormulationEunsol Jeong, Taewhan Kim 0001, Heechun Park. aspdac 2025: 879-885 [doi]

Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA AccelerationZijian Jiang, Keran Zheng, David Boland, Yungang Bao, Kan Shi. aspdac 2025: 1336-1342 [doi]

A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET TechnologyYunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han. aspdac 2025: 338-341 [doi]

RISC-V Driven Orchestration of Vector Processing Units and eFlash Compute-in-Memory Arrays for Fast and Accurate Keyword SpottingGunil Kang, Dahoon Park, Hojin Lee, Sangwoo Jung, Jiyong Park, Jung Gyu Min, Youngjoo Lee, Jaeha Kung. aspdac 2025: 1174-1180 [doi]

Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space ProbesSota Kano, Naoto Usami, Atsushi Tomiki, Tetsuya Iizuka. aspdac 2025: 360-363 [doi]

Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based ModelsWei-Yao Kao, Tai-Jung Lin, Yao-Wen Chang. aspdac 2025: 560-566 [doi]

Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8KTakuma Kawakami, Takashi Sato 0001, Hiromitsu Awano. aspdac 2025: 1438-1443 [doi]

DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled RepresentationsSadaf Khan, Zhengyuan Shi, Ziyang Zheng, Min Li 0019, Qiang Xu 0001. aspdac 2025: 498-504 [doi]

Self-recovery hysteresis control based on-chip SC DC-DC converter robust to load fluctuationKoji Kikuta, Takashi Hisakado, Mahfuzul Islam 0001. aspdac 2025: 348-351 [doi]

Invited paper: Modeling and Simulation of Silicon Photonics Systems in SystemVerilog/XMODELJaeha Kim. aspdac 2025: 141-146 [doi]

Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICsGyumin Kim, Heechun Park. aspdac 2025: 308-314 [doi]

DMCO: A Strategy for Design-Manufacturing Co-optimizationMasaharu Kobayashi. aspdac 2025: 1143 [doi]

Robust Technology-Transferable Static IR Drop Prediction Based on Image-to-Image Machine LearningChao-Chi Lan, Chuan-Chi Su, Yuan-Hsiang Lu, Yao-Wen Chang. aspdac 2025: 1399-1405 [doi]

LIBMixer: An all-MLP Architecture for Cell Library Characterization towards Design Space OptimizationJaeseung Lee, Sunggyu Jang, Jakang Lee, Seokhyeong Kang. aspdac 2025: 814-820 [doi]

A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator SystemsAnkur Limaye, Nicolas Bohm Agostini, Claudio Barone, Vito Giovanni Castellana, Michele Fiorito, Fabrizio Ferrandi, Andres Marquez, Antonino Tumeo. aspdac 2025: 1016-1022 [doi]

ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic AnalysisTsung-Yu Liu, Yen An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng. aspdac 2025: 79-85 [doi]

FPBA: Flexible Percentile-Based Allocation for Multiple-Bits-Per-Cell RRAMJunfei Liu, Anson Kahng. aspdac 2025: 1202-1208 [doi]

A Buffer Reservation Scheduling Strategy for Enhancing Performance of NoC Router BypassingZixuan Liu, Yaoyao Ye. aspdac 2025: 575-580 [doi]

K-Gate Lock: Multi-Key Logic Locking Using Input Encoding Against Oracle-Guided AttacksKevin Lopez, Amin Rezaei 0001. aspdac 2025: 794-800 [doi]

Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge DevicesHiroki Matsutani, Masaaki Kondo, Kazuki Sunaga, Radu Marculescu. aspdac 2025: 51-57 [doi]

Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devicesKenji Mii, Daisuke Kanemoto, Tetsuya Hirose. aspdac 2025: 356-359 [doi]

Ultra Low-power Capacitively-coupled Chopper Amplifier Focusing on the Sparsity of Compressed Sensing for EEG RecordingKenji Mii, Daisuke Kanemoto, Tetsuya Hirose. aspdac 2025: 368-371 [doi]

Cryo-CMOS Analog Circuits for Spin Qubit ControlTakuji Miki. aspdac 2025: 1444-1449 [doi]

Re-Consideration of Correlation Between Interface States and Bulk Traps Using Cryogenic MeasurementYuichiro Mitani, Tatsuya Suzuki, Yohei Miyaki. aspdac 2025: 1432-1437 [doi]

Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural NetworksThai-Hoang Nguyen, Youngjin Ju, Dongsub Yoon, Hyojin Choi. aspdac 2025: 622-627 [doi]

Large-Scale AGV Routing Based on Multi-FPGA SQA AccelerationThinh NguyenQuang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki. aspdac 2025: 1188-1194 [doi]

SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power OptimizationYikang Ouyang, Yuchao Wu, Dongsheng Zuo, Subhendu Roy, Tinghuan Chen, Zhiyao Xie, Yuzhe Ma. aspdac 2025: 1392-1398 [doi]

Theoretical Optimal Specifications of Memcapacitors for Charge-Based In-Memory ComputingZichen Qian, Rentao Wan, Chin-Hsiang Liao, Steven Koester, Mingoo Seok. aspdac 2025: 468-475 [doi]

Making Legacy Hardware Robust against Side Channel Attacks via High-Level SynthesisMd. Imtiaz Rashid, Benjamin Carrión Schäfer. aspdac 2025: 433-439 [doi]

FactorFlow: Mapping GEMMs on Spatial Architectures through Adaptive Programming and Greedy OptimizationMarco Ronzani, Cristina Silvano. aspdac 2025: 706-712 [doi]

An Algebraic Approach to Partial Synthesis of Arithmetic CircuitsBhavani Sampathkumar, Ritaja Das, Bailey Martin, Florian Enescu, Priyank Kalla. aspdac 2025: 1097-1103 [doi]

Advanced Packaging Technology and Design Methodology for Next Generation ChipletsHideki Sasaki. aspdac 2025: 1144 [doi]

Efficient and Secure Cloud-based Split Logic SynthesisChaitali Sathe, Yiorgos Makris, Benjamin Carrión Schäfer. aspdac 2025: 1282-1287 [doi]

ML for Computational Lithography: Practical RecipesYoungsoo Shin. aspdac 2025: 690-692 [doi]

HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAsQilin Si, Benjamin Carrión Schäfer. aspdac 2025: 272-278 [doi]

GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist RasterizationYiyang Sun, Peiran Yan, Yiqi Jing, Le Ye, Tianyu Jia. aspdac 2025: 1379-1385 [doi]

Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal SchedulingDaniel Bochen Tan, Wan-Hsuan Lin, Jason Cong. aspdac 2025: 921-929 [doi]

OPL4GPT: An Application Space Exploration of Optimal Programming Language for Hardware Design by LLMKimia Tasnia, Sazadur Rahman. aspdac 2025: 981-987 [doi]

Hardware Synthesizable Exceptions using ContinuationsPaul Teng, Christophe Dubach. aspdac 2025: 1104-1111 [doi]

ResCap: Fast-yet-Accurate Capacitance Extraction for Standard Cell Design by Physics-Guided Machine LearningJiun-Cheng Tsai, Hsuan-Ming Huang, Wei-Min Hsu, Pei-Ting Lee, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, Charles H.-P. Wen. aspdac 2025: 1243-1250 [doi]

Via Fabrication with Multi-Row Guiding Templates Using Lamellar DSAYun-Na Tsai, Shao-Yun Fang. aspdac 2025: 1386-1391 [doi]

Raads: Rapidus's AI/ML based assisted design flow to reduce design period halvedKoki Tsurusaki. aspdac 2025: 1142 [doi]

LightCL: Compact Continual Learning with Low Memory Footprint For Edge DeviceZeqing Wang, Fei Cheng, Kangye Ji, Bohu Huang. aspdac 2025: 43-50 [doi]

A Fail-Slow Detection Framework for HBM DevicesZikang Xu, Yiming Zhang 0003, Zhirong Shen. aspdac 2025: 491-497 [doi]

A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25-71GHz for Multi-Band 5G NRDongfan Xu, Minzhe Tang, Yi Zhang 0092, Zheng Li 0021, Jian Pang, Atsushi Shirane, Kenichi Okada 0001. aspdac 2025: 352-353 [doi]

Efficient ML-Based Transient Thermal Prediction for 3D-ICsYun-Feng Yang, Wei-Shen Wang, Yung-Jen Lee, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying Shiun Li, Jessica Yen, Lang Lin. aspdac 2025: 628-634 [doi]

Automated Power-saving User-interfaces for Application DesignersHuan-Chun Yeh, Yu-Zheng Su, Chun-Han Lin. aspdac 2025: 601-606 [doi]

ParaFormer: A Hybrid Graph Neural Network and Transformer Approach for Pre-Routing Parasitic RC PredictionJongho Yoon, Jakang Lee, Donggyu Kim, Junseok Hur, Seokhyeong Kang. aspdac 2025: 513-519 [doi]

Enhanced Operator Learning for Scalable and Ultra-fast Thermal Simulation in 3D-IC DesignXinling Yu, Ziyue Liu 0003, Hai Li 0008, Ian A. Young, Zheng Zhang 0005. aspdac 2025: 113 [doi]

Back-end-aware Fault-tolerant Quantum Oracle SynthesisMingfei Yu, Alessandro Tempia Calvino, Mathias Soeken, Giovanni De Micheli. aspdac 2025: 930-937 [doi]

Deep Learning Inspired Capacitance Extraction TechniquesWenjian Yu, Shan Shen, Dingcheng Yang, Haoyuan Li, Jiechen Huang, Chunyan Pei. aspdac 2025: 106-112 [doi]

DefectTrackNet: Efficient Root Cause Analysis of Wafer Defects in Semiconductor Manufacturing Using a Lightweight CNN-Transformer ArchitectureLichao Zeng, Zhouzhouzhou Mei, Zhongyu Shi, Yining Chen. aspdac 2025: 821-827 [doi]

3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric ControlYushen Zhang, Dragan Raseta, Tsun-Ming Tseng, Ulf Schlichtmann. aspdac 2025: 1357-1363 [doi]

Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer OptimizationsQijun Zhang, Zhiyao Xie. aspdac 2025: 1062-1069 [doi]

In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence AnalysisYou-Kai Zheng, Ming-Liang Wei, Hsiang-Yun Cheng, Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong, Po-Hao Tseng, Hsiang-Pang Li. aspdac 2025: 1008-1015 [doi]

A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip TopologiesZhidan Zheng, You-Jen Chang, Liaoyuan Cheng, Tsun-Ming Tseng, Ulf Schlichtmann. aspdac 2025: 1372-1378 [doi]

MACO: A HW-Mapping Co-optimization Framework for DNN AcceleratorsWujie Zhong, Zijun Jiang, Yangdi Lyu. aspdac 2025: 1-7 [doi]

Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR ApplicationsZhiwei Zhong, Yijie Wei, Lance Christopher Go, Yiqi Li, Jie Gu 0001. aspdac 2025: 317-320 [doi]

Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave DetectionYuyang Zhu, Zunsong Yang, Zhenyu Cheng 0003, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka. aspdac 2025: 344-347 [doi]

A Holistic FPGA Architecture Exploration Framework for Deep Learning AccelerationJiadong Zhu, Dongsheng Zuo, Yuzhe Ma. aspdac 2025: 1048-1054 [doi]

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