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2009

Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete, editors, ACM, 2009. [doi]

PSMalloc: content based memory management for MPI applicationsSusmit Biswas, Diana Franklin, Timothy Sherwood, Frederic T. Chong, Bronis R. de Supinski, Martin Schulz 0001. medea 2009: 43-48 [doi]

Temperature reduction analysis in Sentry Tag cache systemsMostafa Farahani, Amirali Baniasadi. medea 2009: 22-27 [doi]

Achieving high memory performance from heterogeneous architectures with the SARC programming modelRoger Ferrer, Vicenç Beltran0001, Marc González, Xavier Martorell, Eduard Ayguadé. medea 2009: 15-21 [doi]

Performance balancing: software-based on-chip memory management for effective CMP executionsNaoto Fukumoto, Kenichi Imazato, Koji Inoue, Kazuaki J. Murakami. medea 2009: 28-34 [doi]

Performance tuning and analysis of future vector processors based on the roofline modelYoshiei Sato, Ryu-ichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi. medea 2009: 7-14 [doi]

Memory management thread for heap allocation intensive sequential applicationsDevesh Tiwari, Sanghoon Lee 0006, James Tuck, Yan Solihin. medea 2009: 35-42 [doi]

2008

Evaluation of memory performance on the cell BE with the SARC programming modelRoger Ferrer, Marc González, Federico Silla, Xavier Martorell, Eduard Ayguadé. medea 2008: 77-84 [doi]

Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi, editors, ACM, 2008. [doi]

Accurate system-level performance modeling and workload characterization for mobile internet devicesMitchell Hayenga, Chander Sudanthi, Mrinmoy Ghosh, Prakash Ramrakhyani, Nigel C. Paver. medea 2008: 54-60 [doi]

Zero loads: canceling load requests by tracking zero valuesMafijul Md. Islam, Per Stenström. medea 2008: 16-23 [doi]

A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 cachesHyunhee Kim, Sungjun Youn, Jihong Kim 0001. medea 2008: 30-37 [doi]

Modeling of cache access behavior based on Zipf's lawIsao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. medea 2008: 9-15 [doi]

Version management alternatives for hardware transactional memoryMarc Lupon, Grigorios Magklis, Antonio González 0001. medea 2008: 69-76 [doi]

PFetch: software prefetching exploiting temporal predictability of memory access streamsJaydeep Marathe, Frank Mueller 0001. medea 2008: 1-8 [doi]

Predictable dynamic instruction scratchpad for simultaneous multithreaded processorsStefan Metzlaff, Sascha Uhrig, Jörg Mische, Theo Ungerer. medea 2008: 38-45 [doi]

A shared cache for a chip multi vector processorAkihiro Musa, Yoshiei Sato, Takashi Soga, Koki Okabe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. medea 2008: 24-29 [doi]

Exploiting multithreaded architectures to improve the hash join operationLayali K. Rashid, Wessam M. Hassanein, Moustafa A. Hammad. medea 2008: 46-53 [doi]

WormBench: a configurable workload for evaluating transactional memory systemsFerad Zyulkyarov, Adrián Cristal, Sanja Cvijic, Eduard Ayguadé, Mateo Valero, Osman S. Unsal, Tim Harris 0001. medea 2008: 61-68 [doi]

2007

Improving disk bandwidth-bound applications through main memory compressionVicenç Beltran 0001, Jordi Torres, Eduard Ayguadé. medea 2007: 57-63 [doi]

Analysis of static and dynamic energy consumption in NUCA caches: initial resultsAlessandro Bardine, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete. medea 2007: 105-112 [doi]

Characterization of Apache web server with Specweb2005Ana Bosque, Pablo Ibáñez, Víctor Viñals, Per Stenström, José María Llabería. medea 2007: 65-72 [doi]

Broadcast filtering-aware task assignment techniques for low-power MPSoCsChun-Mok Chung, Jihong Kim 0001. medea 2007: 89-96 [doi]

Code-size conscious pipelining of imperfectly nested loopsMohammed Fellahi, Albert Cohen 0001, Sid Ahmed Ali Touati. medea 2007: 49-55 [doi]

Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007Pierfrancesco Foglia, Cosimo Antonio Prete, Sandro Bartolini, Roberto Giorgi, editors, ACM, 2007. [doi]

Reducing leakage in power-saving capable caches for embedded systems by using a filter cacheRoberto Giorgi, Paolo Bennati. medea 2007: 97-104 [doi]

A power-aware shared cache mechanism based on locality assessment of memory reference for CMPsIsao Kotera, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. medea 2007: 113-120 [doi]

Building a large instruction window through ROB compressionFernando Latorre, Grigorios Magklis, José González 0002, Pedro Chaparro, Antonio González 0001. medea 2007: 41-48 [doi]

Multithreaded software transactional memory and OpenMPMilos Milovanovic, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero. medea 2007: 81-88 [doi]

An on-chip cache design for vector processorsAkihiro Musa, Yoshiei Sato, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi. medea 2007: 17-23 [doi]

Parallelization schemes for memory optimization on the cell processor: a case study of image processing algorithmTarik Saidani, Stéphane Piskorski, Lionel Lacassagne, Samir Bouaziz. medea 2007: 9-16 [doi]

Improving the accuracy of snoop filtering using stream registersValentina Salapura, Matthias A. Blumrich, Alan Gara. medea 2007: 25-32 [doi]

The STAPL pArrayGabriel Tanase, Mauro Bianco, Nancy M. Amato, Lawrence Rauchwerger. medea 2007: 73-80 [doi]

Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocationAkihiro Yamamoto, Yusuke Tanaka 0001, Hideki Ando, Toshio Shimada. medea 2007: 33-40 [doi]

2006

Proceedings of the 2006 workshop on MEmory performance - DEaling with Applications, systems and architectures, MEDEA '06, Seattle, Washington, USA, September 16-20, 2006ACM, 2006. [doi]

Investigating cache energy and latency break-even points in high performance processorsKaveh Jokar Deris, Amirali Baniasadi. medea 2006: 13-20 [doi]

An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor cachesHaakon Dybdahl, Per Stenström, Lasse Natvig. medea 2006: 45-52 [doi]

Analyzing block locality in Morton-order and Morton-hybrid matricesK. Patrick Lorton, David S. Wise. medea 2006: 5-12 [doi]

Data prefetching in a cache hierarchy with high bandwidth and capacityLuis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals. medea 2006: 37-44 [doi]

A simple speculative load control mechanism for energy savingTanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero. medea 2006: 29-36 [doi]

Evaluating instruction cache vulnerability to transient errorsJun Yan, Wei Zhang. medea 2006: 21-28 [doi]

2004

Guests editor's introductionmedea 2004: 1-2 [doi]

SH-X: an embedded processor core for consumer appliancesFumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori. medea 2004: 33-40 [doi]

Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004Sandro Bartolini, Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete, editors, ACM, 2004. [doi]

Energy aware memory architecture configurationHanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin. medea 2004: 3-9 [doi]

Locality analysis to control dynamically way-adaptable cachesHiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa. medea 2004: 25-32 [doi]

Improving data cache performance with integrated use of split caches, victim cache and stream buffersAfrin Naz, Mehran Rezaei, Krishna Kavi, Philip H. Sweany. medea 2004: 41-48 [doi]

Speculative execution for hiding memory latencyAlex Pajuelo, Antonio González 0001, Mateo Valero. medea 2004: 49-56 [doi]

DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latencyHyo-Joong Suh, Sung Woo Chung. medea 2004: 10-16 [doi]

The impact of traffic aggregation on the memory performance of networking applicationsJavier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero. medea 2004: 57-62 [doi]

Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratiosSami Yehia, Jean-Francois Collard, Olivier Temam. medea 2004: 17-24 [doi]

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