| 0 | -- | 0 | N. Ranganathan, Sharad C. Seth. Conference Reports |
| 3 | -- | 4 | Ajit M. Prabhu. Management Perspectives in EDA |
| 6 | -- | 7 | Ben Bennetts. Guest Editor s Introduction |
| 8 | -- | 15 | Robert C. Aitken. An Overview of Test Synthesis Tools |
| 16 | -- | 23 | Henry Cox. Synthesizing Circuits with Implicit Testability Constraints |
| 24 | -- | 31 | Kwang-Ting (Tim) Cheng. Single-Clock Partial Scan |
| 32 | -- | 39 | Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly. Testability Implications of Performance-Driven Logic Synthesis |
| 40 | -- | 41 | Charles F. Hawkins, Jerry M. Soden. IDDQ Design and Test Advantages Propel Industry |
| 42 | -- | 52 | Don Douglas Josephson, Mark Storey, Daniel D. Dixon. Microprocessor IDDQ Testing: A Case Study |
| 53 | -- | 59 | Mick Tegethoff, Kenneth P. Parker. IEEE Std 1149.1: Where Are We? Where From Here? |
| 60 | -- | 69 | Robert A. Walker, Samit Chaudhuri. Introduction to the Scheduling Problem |
| 70 | -- | 80 | Mustapha Slamani, Bozena Kaminska. Multifrequency Analysis of Faults in Analog Circuits |
| 82 | -- | 0 | Luc J. M. Claesen. ED&TC 1995: Simulation versus formal verification |
| 84 | -- | 0 | Joe Damore. Design Automation Technical Committee Newsletter |