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    Journal: IEEE Design & Test of Computers

    Volume 12, Issue 4

    4 -- 0Ajit M. Prabhu. The EDA Business Model Dialogue Part 2
    6 -- 7Frederick L. Kitson. Guest Editor s Introduction: Multimedia Drives Changes
    8 -- 17Frederick L. Kitson, Vasudev Bhaskaran, Devendra Kalra. Transitioning Desktops to Set Tops
    18 -- 27Jihong Kim, Yongmin Kim. Simulating Multimedia Systems with MVPSIM
    28 -- 33Christian J. Van Den Branden Lambrecht, Vasudev Bhaskaran, Al Kovalick, Murat Kunt. Automatically Assessing MPEG Coding Fidelity
    34 -- 44David K. Fibush. Testing Multimedia Transmission Systems
    45 -- 51Manoj Sachdev. Testing Defects in Scan Chains
    52 -- 59Jing-Yang Jou, Kwang-Ting (Tim) Cheng. Timing-Driven Partial Scan
    60 -- 67Eugeni Isern, Joan Figueras. IDDQ Test and Diagnosis of CMOS Circuits
    68 -- 80Randall Mcree. Testing and Diagnosing Managed Networks
    81 -- 83Bulent I. Dervisoglu. Special Report: Shared-I/O Scan Test
    84 -- 90. A D&T Roundtable: Low-Power Design
    91 -- 94. IEEE Design & Test of Computers Annual Index, Volume 12
    95 -- 97Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois. Conference Reports
    100 -- 101. Design Automation Technical Committee Newsletter
    102 -- 103. Test Technology TC Newsletter

    Volume 12, Issue 3

    0 -- 105. New Products
    4 -- 0R. I. Campbell. Panel Summaries
    6 -- 0Ajit M. Prabhu. The EDA Business Model Dialogue Part 1
    10 -- 0. Conference Reports
    12 -- 13Teruhiko Yamada. Accelerating the Pace of R&D in Asia
    14 -- 23Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen. Identifying Untestable Faults in Sequential Circuits
    24 -- 32Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. Concurrent Error Detection Using Monitoring Machines
    34 -- 42Yoshiaki Kakuda, Hideki Yukitomo, Shinji Kusumoto, Tohru Kikuno. Localizing Multiple Faults in a Protocol Implementation
    44 -- 52Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu. Multiple Fault Diagnosis by Sensitizing Input Pairs
    53 -- 61Keith Baker, Alan Hales. Plug-and-Play IDDQ Testing for Test Fixtures
    62 -- 69Kenneth M. Wallquist. Achieving IDDQ/ISSQ Production Testing with QuiC-Mon
    70 -- 84Nand Kumar, Srinivas Katkoori, Leo Rader, Ranga Vemuri. Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
    86 -- 95Paolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina. Industrial BIST of Embedded RAMs
    96 -- 102. A D&T Roundtable: The Practical Application of Formal Verification
    108 -- 109. Design Automation Technical Committee Newsletter
    110 -- 111. Test Technology TC Newsletter

    Volume 12, Issue 2

    0 -- 0N. Ranganathan, Sharad C. Seth. Conference Reports
    3 -- 4Ajit M. Prabhu. Management Perspectives in EDA
    6 -- 7Ben Bennetts. Guest Editor s Introduction
    8 -- 15Robert C. Aitken. An Overview of Test Synthesis Tools
    16 -- 23Henry Cox. Synthesizing Circuits with Implicit Testability Constraints
    24 -- 31Kwang-Ting (Tim) Cheng. Single-Clock Partial Scan
    32 -- 39Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly. Testability Implications of Performance-Driven Logic Synthesis
    40 -- 41Charles F. Hawkins, Jerry M. Soden. IDDQ Design and Test Advantages Propel Industry
    42 -- 52Don Douglas Josephson, Mark Storey, Daniel D. Dixon. Microprocessor IDDQ Testing: A Case Study
    53 -- 59Mick Tegethoff, Kenneth P. Parker. IEEE Std 1149.1: Where Are We? Where From Here?
    60 -- 69Robert A. Walker, Samit Chaudhuri. Introduction to the Scheduling Problem
    70 -- 80Mustapha Slamani, Bozena Kaminska. Multifrequency Analysis of Faults in Analog Circuits
    82 -- 0Luc J. M. Claesen. ED&TC 1995: Simulation versus formal verification
    84 -- 0Joe Damore. Design Automation Technical Committee Newsletter

    Volume 12, Issue 1

    2 -- 4. EIC Message
    5 -- 0Ajit M. Prabhu. Managing your EDA investments
    7 -- 0. Call for Articles
    8 -- 9. News
    12 -- 0Vinod K. Agarwal. VTS 1994 Panel Report on BIST for Consumer Products
    13 -- 0Tam Anh Chu, Rabindra K. Roy. Guest Editors Introduction: More Practical Asynchronous Design
    14 -- 23Victor Varshavsky, Vyacheslav Marakhovsky, Vadim V. Smolensky. Designing Self-Timed Devices Using the Finite Automaton Model
    24 -- 31Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger. Automatic Verification of Asynchronous Circuits
    31 -- 0. Call for Articles
    32 -- 40Alexandre Yakovlev, Albert Koelmans, Luciano Lavagno. High-Level Modeling and Design of Asynchronous Interface Logic
    41 -- 52Shoab Ahmed Khan, Vijay K. Madisetti. System Partitioning of MCMs for Low Power
    53 -- 67Daniel D. Gajski, Frank Vahid. Specification and Design of Embedded Hardware-Software Systems
    68 -- 74Yuejian Wu, André Ivanov. Reducing Hardware with Fuzzy Multiple Signature Analysis
    75 -- 82. A D&T Roundtable: Test Benchmarking
    85 -- 86. Author Guidelines: IEEE Design & Test of Computers
    87 -- 89. New Products
    91 -- 92. DATC Newsletter
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