Journal: IEEE Design & Test of Computers

Volume 24, Issue 5

412 -- 0Tim Cheng. Combining synchronous and asynchronous timing schemes for high-performance systems
414 -- 416Michael Kishinevsky, Sandeep K. Shukla, Ken S. Stevens. Guest Editors Introduction: GALS Design and Validation
418 -- 428Paul Teehan, Mark R. Greenstreet, Guy Lemieux. A Survey and Taxonomy of GALS Design Styles
430 -- 441Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet. Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
442 -- 452Mario R. Casu, Luca Macchiarulo. Adaptive Latency-Insensitive Protocols
454 -- 463Luis A. Plana, Stephen B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang. A GALS Infrastructure for a Massively Parallel Multiprocessor
464 -- 472Tejpal Singh, Alexander Taubin. A Highly Scalable GALS Crossbar Using Token Ring Arbitration
474 -- 475Anne Gattiker. Guest Editor s Introduction: Getting More Out of Test
476 -- 485Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai. X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
486 -- 493Mack W. Riley, Mike Genden. Cell Broadband Engine Debugging for Unknown Events
494 -- 501Scott Davidson, Helen Davidson. The Psychology of Electronic Test
502 -- 504Sachin S. Sapatnekar, Leon Stok. DAC Highlights
505 -- 0Joe Damore. DATC Newsletter
506 -- 507Scott Davidson. Book Reviews: Test Tutorials in Book Form
510 -- 0Erik Jan Marinissen, Axel Jantsch, Nicola Nicolici. DATE 07 workshop on diagnostic services in NoCs
511 -- 0Bruce C. Kim. TTTC Newsletter
512 -- 0Jill Sibert. ITC exhibits for fun and profit