| 501 | -- | 512 | Richard L. Taylor. A Software Architecture for a Mature Design Automation System |
| 512 | -- | 523 | Ronald B. Capelli, George C. Sax. A Device-Independent Graphics Package for CAD Applications |
| 524 | -- | 537 | Walter H. Elder, Peter P. Zenewicz, Rita R. Alvarodiaz. An Interactive System for VLSI Chip Physical Design |
| 537 | -- | 545 | John A. Darringer, Daniel Brand, John V. Gerbi, William H. Joyner Jr., Louise Trevillyan. LSS: A System for Production Logic Synthesis |
| 546 | -- | 556 | James L. Gilkinson, Steven D. Lewis, Bruce B. Winter, Amir Hekmatpour. Automated Technology Mapping |
| 557 | -- | 563 | Leon I. Maissel, Hillel Ofek. Hardware Design and Description Languages in IBM |
| 564 | -- | 571 | Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman. Using a Hardware Simulation Engine for Custom MOS Structured Designs |
| 572 | -- | 580 | Rolf-Dieter Fiebrich, Yuh-Zen Liao, George M. Koppelman, Edward N. Adams. PSI: A Symbolic Layout System |
| 581 | -- | 589 | Peter W. Cook. Constraint Solver for Generalized IC Layout |
| 590 | -- | 595 | A. M. Barone, J. K. Morrell. Custom Chip/Card Design System |
| 596 | -- | 602 | Peter S. Hauge, Ellen J. Yoffa. ACORN: A System for CVS Macro Design by Tree Placement and Tree Customization |
| 603 | -- | 612 | Peter C. Elmendorf. KWIRE: A Multiple-Technology, User-Reconfigurable Wiring Tool for VLSI |
| 613 | -- | 624 | Ralph Linsker. An Iterative-Improvement Penalty-Function-Driven Wire Routing System |
| 625 | -- | 635 | D. Leet, P. Shearon, R. France. A CMOS LSSD Test Generation System |
| 636 | -- | 640 | Charles H. Stapper. Yield Model for Fault Clusters Within Integrated Circuits |