Journal: IEEE Transactions on Computers

Volume 28, Issue 9

594 -- 601Suhas S. Patil, Terry A. Welch. A Programmable Logic Approach for VLSI
602 -- 608Roy A. Wood. A High Density Programmable Logic Array Chip
609 -- 617Yahiko Kambayashi. Logic Design of Programmable Logic Arrays
617 -- 627Daniel L. Ostapko, Se June Hong. Fault Analysis and Test Generation for Programmable Logic Arrays (PLA s)
627 -- 636Share Young Lee, Hsu Chang. Associative-Search Bubble Devices for Content-Addressable Memory and Array Logic
637 -- 642Heinrich Pangratz, Hans Weinrichter. Pseudo-Random Number Generator Based on Binary and Quinary Maximal-Length Sequences
643 -- 647Jon Louis Bentley, Thomas Ottmann. Algorithms for Reporting and Counting Geometric Intersections
648 -- 659Hung Chi Lai, Saburo Muroga. Minimum Parallel Binary Adders with NOR (NAND) Gates
660 -- 670Utpal Banerjee, Shyh-Ching Chen, David J. Kuck, Ross A. Towle. Time and Parallel Processor Bounds for Fortran-Like Loops
671 -- 677Joseph Y.-T. Leung, Edmund K. Lai. On Minimum Cost Recovery from System Deadlock
678 -- 681B. Ramakrishna Rau. Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System
682 -- 685Tsutomu Sasao, Kozo Kinoshita. Conservative Logic Elements and Their Universality
686 -- 690Carl-Erik W. Sundberg. Properties of Transparent Shortened Codes for Memories With Stuck-at Faults
690 -- 691Leslie Lamport. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
691 -- 693Vishwani D. Agrawal. Comments on An Approach to Highly Integrated Computer-Maintained Cellular Arrays
693 -- 0Earl E. Swartzlander Jr.. Comment on The Focus Number System
693 -- 0Samuel C. Lee, Albert D. Edgar. Addendum to The Focus Number System

Volume 28, Issue 8

546 -- 559Edward J. McCluskey. Logic Design of Multivalued I:::2:::L Logic Circuits
560 -- 566Graziano Frosini, Francesco M. Viterbo. An Algorithm for Evaluating the Frequency of a Rotating Vector
567 -- 572Earl E. Swartzlander Jr., Douglas J. Heath. A Routing Algorithm for Signal Processing Networks
573 -- 576Thomas S. Heines. Buffer Behavior in Computer Communication Systems
577 -- 580Arthur R. Butz. FFT Length in Digital Filtering
580 -- 581Paul B. Schneck. Comment on When to Use Random Testing
581 -- 0Vishwani D. Agrawal. Author s Reply
582 -- 586Michael B. Feldman. An Application-Oriented Programming Language for Sequential Machine Studies
586 -- 590Thaddeus Kobylarz, Atef Al-Najjar. An Examination of the Cost Function for Programmable Logic Arrays

Volume 28, Issue 7

461 -- 471G. Robert Redinbo. Finite Field Arithmetic on an Array Processor
472 -- 482Eduard Cerny, Daniel Mange, Eduardo Sanchez. Synthesis of Minimal Binary Decision Trees
483 -- 487Frank Rubin. Decrypting a Stream Cipher Based on ::::J-K:::: Flop-Flops
487 -- 492Irving S. Reed, Trieu-Kien Truong. A New Hybrid Algorithm for Computing a Fast Discrete Fourier Transform
493 -- 500William K. S. Walker, Carl-Erik W. Sundberg, Colin J. Black. A Reliable Spaceborne Memory with a Single Error and Erasure Correction Scheme
500 -- 505Kin-Man Chung, C. K. Wong. Asymtotically Optimal Interconnection Networks from Two-State Cells
514 -- 520Israel Koren, Stephen Y. H. Su. Reliability Analysis of ::::N::::-Modular Redundancy Systems with Intermittent and Permanent Faults
521 -- 528H. Allen Curtis. Short-Cut Method of Deriving Nearly Optimal Arrays of NAND Trees
528 -- 531Warren D. Little, Richard W. Heuft. An Area Shading Graphics Display Systems
531 -- 535A. Dunworth, H. V. Hartog. An Efficient State Minimization Algorithm for Some Special Classes of Incompletetly Specified Sequential Machines
535 -- 537Kewal K. Saluja, E. H. Ong. Minimization of Reed-Muller Canonic Expansion
537 -- 542Sam Toueg, Kenneth Steiglitz. The Design of Small-Diameter Networks by Local Search
542 -- 543Robert Brian Cutler, Saburo Muroga. Comments on Generalization of Consensus Theory and Application to the Minimization of Boolean Functions

Volume 28, Issue 6

381 -- 383Glen G. Langdon Jr.. Database Machines: An Introduction
384 -- 394Amar Mukhopadhyay. Hardware Algorithms for Nonnumeric Computation
395 -- 406David J. DeWitt. DIRECT - A Multiprocessor Organization for Supporting Relational Database Management Systems
406 -- 413Lee A. Hollaar. A Design for a List Merging Network
414 -- 429Jayanta Banerjee, David K. Hsiao, Krishnamurthi Kannan. DBC - A Database Computer for Very Large Databases
430 -- 445Stanley Y. W. Su, Le Huu Nguyen, Ahmed Emam, G. Jack Lipovski. The Architectural Features and Implementation Techniques of the Multicell CASSM
446 -- 458Stewart A. Schuster, H. B. Nguyen, Esen A. Ozkarahan, Kenneth C. Smith. RAP.2 - An Associative Processor for Databases and Its Applications

Volume 28, Issue 5

333 -- 341Alvin M. Despain. Very Fast Fourier Transform Algorithms Hardware for Implementation
342 -- 353F. Gail Gray, Lionel C. C. Shih, Richard A. Thompson. Diagnosis of Faults in Modular Trees
354 -- 361Yuan-Chieh Chow, Walter H. Kohler. Models for Dynamic Load Balancing in a Heterogeneous Multiple Processor System
362 -- 365P. Ciompi, Luca Simoncini. Analysis and Optimal Design of Self-Diagnosable Systems with Repair
365 -- 367. Combinatorial Merging and Huffman s Algorithm
367 -- 371Wolfgang Coy. On the Design of Easily Testable Iterative Systems of Combinational Cells
371 -- 374Teruo Hikita, Hajime Enomoto. On the Number of Multivalued Switching Functions Realizable by Cascades
374 -- 378James E. Smith. Universal System Diagnosis Algorithms

Volume 28, Issue 4

291 -- 299Gururaj S. Rao, Harold S. Stone, T. C. Hu. Assignment of Task in a Distributed Processor System with Limited Memory
300 -- 306Kai Hwang. Global and Modular Two s Complement Cellular Array Multipliers
300 -- 0Iiro Hartimo, Leo Ojala. Comments on A Stable, Two-Multiplies-per-Cycle Algorithm for Digital Generation of Sinusoids in Real Time
306 -- 310Vason P. Srini. Iterative Realization of Multivalued Logic Systems
316 -- 319Edward L. Robertson. Microcode Bit Optimizations is ::::N P::::-Complete
319 -- 325Claudine Turcat, André Verdillon. Symmetry, Automorphism, and Test
325 -- 329O. Yenersoy. Synthesis of Asynchronous Machines Using Minxed-Operation Mode
330 -- 316Jean-Loup Baer, Barbara Koyama. On the Minimization of the Width of the Control Memory of Microprogammed Processors

Volume 28, Issue 3

178 -- 184Janusz A. Brzozowski, Michael Yoeli. On a Ternary Model of Gate Networks
184 -- 190I-Ngo Chen, Paul Y. Chen, Tse-Yun Feng. Associative Processing of Network Flow Problems
191 -- 199B. Ramakrishna Rau. Program Behavior and the Performance of Interleaved Memories
200 -- 204K. Wayne Current, Douglas A. Mow. Implementing Parallel Counters with Four-Valued Threshold Logic
205 -- 214Paul W. Baker. The Solution of Differential Equations on Short-Word-Length Computing Devices
215 -- 224Dharma P. Agrawal. High-Speed Arithmetic Arrays
225 -- 237S. Brent Morris, Arthur Valliere III, Richard A. Wisniewski. Processes for Random and Sequential Accessing in Dynamic Memories
238 -- 243Peter L. Hammer, Uri N. Peled, M. A. Pollatschek. An Algorithm to Dualize a Regular Switching Function
243 -- 244Sargur N. Srihari, Michael K. Ohanesian. An Efficient Algorithm for Determining Hadamard Sequency Vectors
244 -- 249Israel Koren. Analysis of the Signal Reliability Measure and an Evaluation Procedure
249 -- 253Martin Freeman. Aspects of the Upper Bounds of Finite Input-Memory and Finite Output-Memory Sequential Machines
253 -- 255Ronald C. Devries. Comments on A Readily Implemented Single-Error-Correcting Unit-Distance Counting Code
255 -- 257Erik Paaske. Comments on A New Random-Error-Correction Code
257 -- 258John En. Autor s Reply
258 -- 261Ravindra Nair. Comments on An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories
261 -- 262James E. Smith. Comments on Redundancy Testing in Combinational Networks
262 -- 267Prathima Agrawal, Melvin A. Breuer. Experiments with a Density Router for PC Cards
267 -- 268Henry O. Kunz. On the Equivalence Between One-Dimensional Discrete Walsh-Hadamard and Multidimensional Discrete Fourier Transforms
268 -- 269Israel Koren, Zvi Kohavi. On the Properties of Sensitized Paths
269 -- 273J. S. Hill. Revision of the Buffer Length Derivation for a Modified ::::E::k::/D/::::1 Systems by Maritsas and Hartley
273 -- 276Werner Fleischhammer, Osman Dörtok. The Anomalous Behavior of Flip-Flops in Synchronizer Circuits
276 -- 281Michel Diaz, Pierre Azéma, Jean-Michel Ayache. Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines

Volume 28, Issue 2

89 -- 101Alexis C. Arvillias, Dimitris G. Maritsas. Toggle-Registers Generating in Parallel ::::k k::::th Decimations of ::::m::::-Sequences ::::x:::p::::::: + ::::x:::k::::::: + 1 Design Tables
101 -- 109Yaohan Chu. Architecture of a Hardware Data Interpreter
109 -- 120Charles B. Silio Jr.. An Efficient Simplex Coverability Algorithm in ::::E::::::: 2::: with Application to Stochastic Sequential Machines
121 -- 133S. Karunanithi, Arthur D. Friedman. Analysis of Digital Systems Using a New Measure of System Diagnosis
133 -- 141Malcolm C. Easton, Peter A. Franaszek. Use Bit Scanning in Replacement Decisions
142 -- 147Heinrich Niemann, Jürgen Weiss. A Fast-Converging Algorithm for Nonlinear Mapping of High-Dimensional Data to a Plane
147 -- 150David K. Cheng, James J. Liu. A Generalized Orthogonal Transformation Matriz
150 -- 152Herbert Freeman. Algorithm for Generating a Digital Straight Line on a Triangular Grid
153 -- 156Robert D. Braun, Donald D. Givone. An Improved Algorithm for Deriving Checking Experiments
157 -- 163A. S. Sethi, Narsingh Deo. Interference in Multiprocessor Systems with Localized Memory Access Probabilities
163 -- 167George K. Papakonstantinou. Minimization of Modulo-2 Sum of Products
167 -- 172Constantinos Halatsis, Nikolaos Gaitanis. Positive Fail-Safe Realization of Synchronous Sequential Machines
172 -- 175Raouf F. H. Farag. Word-Level Recognition of Cursive Script

Volume 28, Issue 12

879 -- 887Vojin M. Plavsic, Per-Erik Danielsson. Sequential Evaluation of Boolean Functions
888 -- 906Jane W.-S. Liu, Mario Jino. Intelligent Magnetic Bubble Memories and Their Applications in Data Base Management Systems
907 -- 917Howard Jay Siegel. A Model of SIMD Machines and a Comparison of Various Interconnection Networks
918 -- 926Daniel E. Atkins, Shauchi Ong. Time-Component Complexity of Two Approaches to Multioperand Binary Addition
927 -- 929B. Speelpenning, Jürg Nievergelt. A Simple Model of Processor - Resource Utilization in Networks of Communicating Modules
930 -- 934Earl E. Swartzlander Jr.. Microprogrammed Control for Specialized Processors
934 -- 938V. Vlasenko, K. R. Rao. Unified Matrix Treatment of Discrete Transforms
939 -- 941Mischa Schwartz. Throughput and Time Delay Analysis for a Common Queue Configuration in a Multiprocessor Environment
941 -- 943Yuri Breitbart, K. Vairavan. The Computational Complexity of a Class of Minimization Algorithms for Switching Functions
943 -- 944John P. Robinson. Optimum Golomb Rulers
944 -- 0John V. Blankenbaker. Comments on ``Inner Product Computers''

Volume 28, Issue 11

807 -- 810U. I. Gupta, D. T. Lee, Joseph Y.-T. Leung. An Optimal Solution for the Channel-Assignment Problem
811 -- 818Takashi Nanya, Yoshihiro Tohma. Universal Multicode STT State Assignments for Asynchronous Sequential Machines
819 -- 830Paolo Corsini, Graziano Frosini. Properties of the Multidimensional Generalized Discrete Fourier Transform
831 -- 844Ben-Dau Tseng, Graham A. Jullien, William C. Miller. Implementation of FFT Structures Using the Residue Number System
845 -- 853James E. Smith. Detection of Faults in Programmable Logic Arrays
854 -- 862Joseph G. Tront, Donald D. Givone. A Design for Multiple-Valued Logic Gates Based on MESFET s
863 -- 864George Markowsky. Diagnosing Single Faults in Fanout-Free Combinational Circuits
864 -- 865Miron Abramovici, Melvin A. Breuer. On Redundancy and Fault Detection in Sequential Circuits
865 -- 870Vinod K. Agarwal, Gerald M. Masson. Recursive Coverage Projection of Test Sets
871 -- 874Kenneth R. Sloan Jr., Steven L. Tanimoto. Progressive Refinement of Raster Images
874 -- 875Robert Brian Cutler, Saburo Muroga. Comments on Computing Irredundant Normal Forms from Abbreviated Presence Functions

Volume 28, Issue 10

609 -- 703Andrew Hopper, David J. Wheeler. Binary Routing Networks
704 -- 721Steven I. Kartashev, Svetlana P. Kartashev. A Multicomputer System with Dynamic Architecture
721 -- 727I-Ngo Chen, Robert Willoner. An 0(::::n::::) Parallel Multiplier with Bit-Sequential Input and Output
728 -- 736Yasuhito Suenaga, Takahiko Kamae, Tomonori Kobayashi. A High-Speed Algorithm for the Generation of Straight Lines and Circular Arcs
737 -- 747Erol Gelenbe, Kenneth C. Sevcik. Analysis of Update Synchronization for Multiple Copy Data Bases
747 -- 753John B. Kam, George I. Davida. Structured Design of Substitution-Permutation Encryption Networks
754 -- 767Charles R. Kime. An Abstract Model for Digital System Fault Diagnosis
768 -- 772Keijiro Nakamura. Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks
773 -- 782Edmund A. Lamagna. The Complexity of Monotone Networks for Certain Bilinear Forms, Routing Problems, Sorting, and Merging
782 -- 786Teofilo F. Gonzalez. A Note on Open Shop Preemptive Schedules
786 -- 791Pramod K. Varshney. On Analytical Modeling of Intermittent Faults in Digital Systems
791 -- 794K. G. Kulkarni, V. Jayakumar. Ordering of Connections for Automated Routing
795 -- 798Hans P. Moravec. Fully Interconnecting Multiple Computers with Pipelined Sorting Nets
798 -- 801Anil K. Sarje, Nripendra N. Biswas. A New Approach to 2-Asummability Testing
801 -- 802James E. Smith. On Necessary and Sufficient Conditions for Multiple Fault Undetectability
802 -- 804Thomas J. Chaney. Comments on A Note on Synchronizer or Interlock Maloperation
804 -- 0E. Gordon Wormald. Support for T. J. Chaney s Comments on A Note on Synchronizer or Interlock Maloperation
804 -- 805Bella Bose. Comments on Multiple Fault Detection in Combinational Network

Volume 28, Issue 1

2 -- 7David Nassimi, Sartaj Sahni. Bitonic Sort on a Mesh-Connected Parallel Computer
8 -- 15Ashok K. Chandra, C. K. Wong. The Movement and Permutation of Columns in Magnetic Bubble Lattice Files
16 -- 27John A. McPherson, Charles R. Kime. A Two-Level Diagnostic Model for Digital Systems
28 -- 37Kwok-Tung Fung, Hwa C. Torng. On the Analysis of Memory Conflicts and Bus Contentions in a Multiple-Microprocessor System
38 -- 49Alan Jay Smith. An Analytic and Experimental Study of Multiple Channel Controllers
50 -- 52Vinod K. Agarwal, Gerald M. Masson. A Functional Form Approach to Test Set Coverage in Tree Networks
52 -- 56Y. Zisapel, M. Krieger, J. Kella. Detection of Hazards in Combinational Switching Circuits
57 -- 62H. J. Trussel, Bobby R. Hunt. Improved Methods of Maximum ::::a Posteriori:::: Restoration
62 -- 64Brian R. Gaines. Maryanski s Grammatical Inferencer
64 -- 0Fred J. Maryanski, Taylor L. Booth. Authors Reply
65 -- 66Erkki Oja. On the Construction of Projectors Using Products of Elementary Matrices
66 -- 72Tsutomu Sasao, Kozo Kinoshita. On the Number of Fanout-Free Functions and Unate Cascade Functions
72 -- 75Mordechai Ben-Ari. On Transposing Large ::::2:::n::::::: × ::::2:::n::::::: Matrices
76 -- 85Jay Niel Culliney, Ming Huei Young, T. Nakagawa, Saburo Muroga. Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions
85 -- 86R. David, R. Tellez-Giron. Comments on The Error Latency of a Fault in a Sequential Digital Circuit