| 1196 | -- | 1208 | Qi Xu, Wenhao Sun, Song Chen 0001, Yi Kang, Xiaoqing Wen. Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC |
| 1209 | -- | 1221 | Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu 0003. An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization |
| 1222 | -- | 1235 | Zhengqi Gao, Ron Rohrer. Efficient Non-Monte-Carlo Yield Estimation |
| 1236 | -- | 1248 | Ying Wang 0001, Yintao He, Long Cheng 0003, Huawei Li, Xiaowei Li 0001. A Fast Precision Tuning Solution for Always-On DNN Accelerators |
| 1249 | -- | 1263 | Davide Zoni, Luca Cremona, William Fornaciari. Design of Side-Channel-Resistant Power Monitors |
| 1264 | -- | 1275 | Davide Poggi, Thomas Ordas, Alexandre Sarafianos, Philippe Maurine. Checking Robustness Against EM Side-Channel Attacks Prior to Manufacturing |
| 1276 | -- | 1289 | Farzad Niknia, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi. Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips |
| 1290 | -- | 1301 | Yufei Cui, Qiao Li 0001, Tei-Wei Kuo, Chun Jason Xue. Online Rare Category Identification and Data Diversification for Edge Computing |
| 1302 | -- | 1315 | Yi Wang 0003, Jiangfan Huang, Jing Chen, Rui Mao 0001. PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory |
| 1316 | -- | 1329 | Hui Chen, Peng Chen 0027, Jun Zhou, Luan H. K. Duong, Weichen Liu. ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission |
| 1330 | -- | 1343 | Jeongbin Kim, Yongwoon Song, Kyungseon Cho, Hyukjun Lee, Hongil Yoon, Eui-Young Chung. STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment |
| 1344 | -- | 1357 | Yunhui Qiu, Wenbo Yin, Lingli Wang. A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration |
| 1358 | -- | 1370 | Yuke Wang, Boyuan Feng, Gushu Li, Lei Deng 0003, Yuan Xie 0001, Yufei Ding. STPAcc: Structural TI-Based Pruning for Accelerating Distance-Related Algorithms on CPU-FPGA Platforms |
| 1371 | -- | 1385 | Mohammed Abderehman, Jayprakash Patidar, Jay H. Oza, Yom Nigam, T. M. Abdul Khader, Chandan Karfa. FastSim: A Fast Simulation Framework for High-Level Synthesis |
| 1386 | -- | 1399 | Xiaotong Cui, Xing Zhang, Hao Yan, Liang Zhang, Kefei Cheng, Yu Wu, Kaijie Wu 0001. Toward Building and Optimizing Trustworthy Systems Using Untrusted Components: A Graph-Theoretic Perspective |
| 1400 | -- | 1411 | Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek. Reducing LUT Count for Mealy FSMs With Transformation of States |
| 1412 | -- | 1422 | Chia-Chun Lin, Ciao-Syun Lin, You-Hsuen Tsai, Yung-Chih Chen, Chun-Yao Wang. Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization |
| 1423 | -- | 1435 | Rachel Sterneck, Abhishek Moitra, Priyadarshini Panda. Noise Sensitivity-Based Energy Efficient and Robust Adversary Detection in Neural Networks |
| 1436 | -- | 1447 | Gang Li 0015, Zejian Liu, Fanrong Li, Jian Cheng 0001. Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA |
| 1448 | -- | 1452 | Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, Chun-Xun Lin. Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System |
| 1453 | -- | 1466 | Jinwei Zhang, Sheriff Sadiqbatcha, Michael O'Dea, Hussam Amrouch, Sheldon X.-D. Tan. Full-Chip Power Density and Thermal Map Characterization for Commercial Microprocessors Under Heat Sink Cooling |
| 1467 | -- | 1480 | Ming Yang, Wenjian Yu, Mingye Song, Ning Xu 0006. Volume Reduction and Fast Generation of the Precharacterization Data for Floating Random Walk-Based Capacitance Extraction |
| 1481 | -- | 1494 | Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius S. Livramento, Laércio Lima Pilla, Laleh Behjat, José Luís Güntzel. Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning |
| 1495 | -- | 1508 | Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo. PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes |
| 1509 | -- | 1522 | Behnaz Ranjbar, Ali Hosseinghorban, Mohammad Salehi, Alireza Ejlali, Akash Kumar 0001. Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems |
| 1523 | -- | 1536 | Boqian Wang, Zhonghai Lu. Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture |
| 1537 | -- | 1549 | Biresh Kumar Joardar, Aryan Deshwal, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. High-Throughput Training of Deep CNNs on ReRAM-Based Heterogeneous Architectures via Optimized Normalization Layers |
| 1550 | -- | 1562 | Syuan-Hao Sie, Jye-Luen Lee, Yi Ren Chen, Zuo-Wei Yeh, Zhaofang Li, Chih-Cheng Lu, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang. MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks |
| 1563 | -- | 1572 | Jun-Yu Yang, Shi-Yu Huang. Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction |
| 1573 | -- | 1586 | Alireza Mahzoon, Daniel Große, Rolf Drechsler. RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal |
| 1587 | -- | 1591 | Irith Pomeranz. Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis |