| 401 | -- | 412 | Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim. A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping |
| 413 | -- | 421 | Sai Pentapati, Sung Kyu Lim. Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs |
| 422 | -- | 431 | Xiaoxiao Zheng, Mao Ye 0007, Zhiwei Li, Yao Li, Qiuwei Wang, Yiqiang Zhao. A CMOS AFE Array With DC Input Current Cancellation for FMCW LiDAR |
| 432 | -- | 441 | Hongge Li, Yuhao Chen. Hybrid Stochastic Number and Its Neural Network Computation |
| 442 | -- | 454 | Yongqiang Zhang 0006, Jiao Qin, Jie Han 0001, Guangjun Xie. Design of a Stochastic Computing Architecture for the Phansalkar Algorithm |
| 455 | -- | 467 | Sunwoong Kim, Cameron James Norris, James I. Oelund, Rob A. Rutenbar. Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers |
| 468 | -- | 479 | Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi. FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing |
| 480 | -- | 484 | Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu. A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range |
| 485 | -- | 496 | Zhaojun Lu, Xueyan Wang, Md Tanvir Arafin, Haoxiang Yang, Zhenglin Liu, Jiliang Zhang 0002, Gang Qu 0001. An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference |
| 497 | -- | 504 | YaJuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu 0008, Deming Zhang, Xiangshui Miao. In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays |
| 505 | -- | 518 | Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang. HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization |
| 519 | -- | 529 | Si-Huang Liu, Chia-Yi Kuo, Yannan Mo, Tao Su. An Area-Efficient, Conflict-Free, and Configurable Architecture for Accelerating NTT/INTT |
| 530 | -- | 541 | Bofan Chen, Zhiqun Li, Wei Shi, Yan Yao, Zhi-Ying Xia, Bing-Yan Qiu, Hao Ji. A 6-18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS |
| 542 | -- | 551 | Yifei Zheng, Boyu Li, Qianheng Dong, Yutao Ying, Deyuan Song, Jing Zhu 0006, Weifeng Sun, Qinsong Qian, Long Zhang, Sheng Li, Denggui Wang, Jianjun Zhou. S/dt Noise Immunity Enhancement Structure |
| 552 | -- | 563 | Rakesh Varma Rena, Raviteja Kammari, Vijay Shankar Pasupureddi. A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End |
| 564 | -- | 572 | Xingyu Wang, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara. A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement |
| 573 | -- | 586 | Thai-Ha Tran, Duc-Thuan Dam, Ba-Anh Dao, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang. Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm |
| 587 | -- | 591 | Mahsa Zareie, Kamal El-Sankary, Ezz I. El-Masry, Ximing Fu. An Open-Loop VCO-ADC Based on a Linearized Current Control Technique |
| 592 | -- | 596 | Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh. Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs |