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Armin Alaghi, Mahnaz Sadoughi Yarandi, Zainalabedin Navabi. An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing. In 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006. pages 293-298, IEEE, 2006. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A Low Power BIST Architecture for FPGA Look-Up Table TestingEhsan Atoofian, Zainalabedin Navabi. vlsi 2003: 394-397 A BIST Architecture for FPGA Look-Up Table Testing Reduces ReconfigurationsEhsan Atoofian, Zainalabedin Navabi. ats 2003: 84-89 [doi] An Optimized BIST Architecture for FPGA Look-Up Table TestingMahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi. isvlsi 2006: 420-421 [doi] A Test Approach for Look-Up Table Based FPGAsEhsan Atoofian, Zainalabedin Navabi. jcst, 21(1):141-146, 2006. [doi]
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