The following publications are possibly variants of this publication:
- A Variable Grain Logic Cell Architecture for Reconfigurable Logic CoresMotoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi. fpl 2007: 550-553 [doi]
- A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP CoreKazuki Inoue, Qian Zhao, Yasuhiro Okamoto, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. trets, 4(1):5, 2010. [doi]
- A Novel Local Interconnect Architecture for Variable Grain Logic CellKazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. arc 2009: 97-109 [doi]
- Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology MappingKazunori Matsuyama, Motoki Amagasaki, Hideaki Nakayama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi. arc 2007: 142-154 [doi]
- An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell ArchitectureYoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi. fpt 2007: 241-244 [doi]
- An Embedded Reconfigurable IP Core with Variable Grain Logic Cell ArchitectureMotoki Amagasaki, Ryoichi Yamaguchi, Masahiro Koga, Masahiro Iida, Toshinori Sueyoshi. ijrc, 2008, 2008. [doi]
- COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area MinimizationYasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. fpl 2010: 304-309 [doi]