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Ehsan Atoofian, Zainalabedin Navabi. A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations. In 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China. pages 84-89, IEEE Computer Society, 2003. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A Low Power BIST Architecture for FPGA Look-Up Table TestingEhsan Atoofian, Zainalabedin Navabi. vlsi 2003: 394-397 An Optimized BIST Architecture for FPGA Look-Up Table TestingMahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi. isvlsi 2006: 420-421 [doi] An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table TestingArmin Alaghi, Mahnaz Sadoughi Yarandi, Zainalabedin Navabi. ats 2006: 293-298 [doi] A Test Approach for Look-Up Table Based FPGAsEhsan Atoofian, Zainalabedin Navabi. jcst, 21(1):141-146, 2006. [doi]
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