The following publications are possibly variants of this publication:
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- Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size CharacteristicShuo-Han Chen, Yen-Ting Chen, Hsin-Wen Wei, Wei Kuan Shih. dac 2017: [doi]
- Nimble Mapping SSD: Leaning State Mapping Strategy to Increase Reliability of 3D TLC Charge-Trap NAND Flash MemoryChih-Chia Chen, Jen-Wei Hsieh. nvmsa 2022: 57-62 [doi]
- Enabling sub-blocks erase management to boost the performance of 3D NAND flash memoryTseng-Yi Chen, Yuan-Hao Chang, Chien-Chung Ho, Shuo-Han Chen. dac 2016: 92 [doi]
- Large Suppression to Lateral Charge Migration (LCM) Related Error Bits in Charge-Trap TLC 3D NAND FlashKenie Xie, Pena Guo, Fei Chen, Binglu Chen, Xiaotong Fang, Jixuan Wu, Xuepeng Zhan, Jiezhi Chen. icta3 2022: 24-25 [doi]
- Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash MemoryFei Wang, Yuan Li, Xiaolei Ma, Jiezhi Chen. access, 9:47391-47398, 2021. [doi]