The following publications are possibly variants of this publication:
- ESD protection design for wideband RF applications in 65-nm CMOS processLi-Wei Chu, Chun-Yu Lin, Ming-Dou Ker, Ming-Hsiang Song, Jeng-Chou Tseng, Chewnpu Jou, Ming-Hsien Tsai. iscas 2014: 1480-1483 [doi]
- Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS processChun-Yu Lin, Li-Wei Chu, Ming-Dou Ker. mr, 51(8):1315-1324, 2011. [doi]
- ESD protection design for CMOS RF integrated circuits using polysilicon diodesMing-Dou Ker, Chyh-Yih Chang. mr, 42(6):863-872, 2002. [doi]
- Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]
- On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS ProcessMing-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang. iscas 2009: 2281-2284 [doi]
- ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCRMing-Dou Ker, Chun-Yu Lin, Guo-Xuan Meng. iscas 2008: 1292-1295 [doi]
- ESD protection design for high-speed applications in CMOS technologyJie-Ting Chen, Chun-Yu Lin, Rong-Kun Chang, Ming-Dou Ker, Tzu-Chien Tzeng, Tzu-Chiang Lin. mwscas 2016: 1-4 [doi]