An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing, 22(2):161-172, 2006. [doi]

This author has not been identified. Look up 'Patrick Girard' in GoogleThis author has not been identified. Look up 'Olivier Héron' in GoogleThis author has not been identified. Look up 'Serge Pravossoudovitch' in GoogleThis author has not been identified. Look up 'Michel Renovell' in Google

runs on WebDSL