Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing, 22(2):161-172, 2006. [doi]
@article{GirardHPR06,
title = {An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs},
author = {Patrick Girard and Olivier Héron and Serge Pravossoudovitch and Michel Renovell},
year = {2006},
doi = {10.1007/s10836-005-4631-1},
url = {http://dx.doi.org/10.1007/s10836-005-4631-1},
tags = {architecture, logic},
researchr = {https://researchr.org/publication/GirardHPR06},
cites = {0},
citedby = {0},
journal = {J. Electronic Testing},
volume = {22},
number = {2},
pages = {161-172},
}