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Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing, 22(2):161-172, 2006. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAsPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. iolts 2004: 187-192 [doi] Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAsPatrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. ets 2004: 52-57 [doi]
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