An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs - researchr publication references

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Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing, 22(2):161-172, 2006. [doi]

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