The following publications are possibly variants of this publication:
- Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential CircuitsYoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita. et, 16(5):443-451, 2000. [doi]
- Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential CircuitsYoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita. ats 1999: 141-146 [doi]
- Static test compaction for IDDQ testing of bridging faults in sequential circuitsYoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita. scjapan, 31(11):41-50, 2000. [doi]
- Efficient Techniques for Reducing IDDQ Observation Time for Sequential CircuitsYoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita. vlsid 1999: 72-77
- Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential CircuitsYoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita. ats 1998: 312-317 [doi]
- A BIST Circuit for IDDQ TestsMasaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita. ats 2003: 390-395 [doi]