High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems - researchr publication related

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Tsuyoshi Isshiki, Wayne Wei-Ming Dai. High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems. In FPGA. pages 167-173, 1995. [doi]

The following publications are possibly variants of this publication:

FPGA for High-Performance Bit-Serial Pipeline DatapathTsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda. aspdac 1998: 331-332

A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract)Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda. fpga 1998: 255 [doi]

Bit-serial pipeline synthesis for multi-FPGA systems with C++ design captureTsuyoshi Isshiki, Wayne Wei-Ming Dai. fccm 1996: 38-47 [doi]

New FPGA Architecture for Bit-Serial Pipeline DatapathAkihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda. fccm 1998: 58-67 [doi]

Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing SystemsKatsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne Wei-Ming Dai. fccm 2000: 339-340 [doi]

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