The following publications are possibly variants of this publication:
- Two phase clocking subthreshold adiabatic logicKazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine. iscas 2014: 598-601 [doi]
- 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XORNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. vlsi 2010: 364-368 [doi]
- Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logicKazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine. apccas 2014: 495-498 [doi]
- A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logicKazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine. newcas 2015: 1-4 [doi]
- Two phase clocked adiabatic static CMOS logicNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. issoc 2009: 83-86 [doi]
- Fundamental logics based on two phase clocked adiabatic static CMOS logicNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. icecsys 2009: 503-506 [doi]
- 2PADCL: Two Phase drive Adiabatic Dynamic CMOS LogicYasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama. apccas 2006: 1484-1487 [doi]