The following publications are possibly variants of this publication:
- Design on ESD Protection Circuit with Very Low and Constant Input CapacitanceTung-Yang Chen, Ming-Dou Ker. isqed 2001: 247-248 [doi]
- Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applicationsMing-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, Hun-Hsien Chang. iscas 2000: 61-64 [doi]
- Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS processYuan-Wen Hsiao, Ming-Dou Ker. mr, 49(6):650-659, 2009. [doi]
- ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring ICChia-Tsen Dai, Ming-Dou Ker. socc 2015: 380-383 [doi]
- Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]
- Current-mode dual-output ICCII-based tunable universal biquadratic filter with low-input and high-output impedancesHua-Pin Chen. ijcta, 42(4):376-393, 2014. [doi]
- ESD protection design for IC with power-down-mode operationMing-Dou Ker, Kun-Hsien Lin. iscas 2004: 717-720
- Mixed-mode ESD protection circuit simulation-design methodologyHaigang Feng, Rouying Zhan, Qiong Wu, Guang Chen, Xiaokang Guan, Haolu Xie, Albert Z. Wang. iscas 2003: 652-655 [doi]