The following publications are possibly variants of this publication:
- IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale IntegrationMeng Lu, Yvon Savaria, Bing Qiu, Jacques Taillefer. dft 2003: 18-25 [doi]
- Design and validation of a novel reconfigurable and defect tolerant JTAG scan chainYves Blaquière, Yan Basile-Bellavance, Safa Berrima, Yvon Savaria. iscas 2014: 2559-2562 [doi]
- Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuitsSafa Berrima, Yves Blaquière, Yvon Savaria. integration, 62:159-169, 2018. [doi]