The following publications are possibly variants of this publication:
- Design of multioutput CMOS combinational logic circuits for robust testabilitySandip Kundu. tcad, 8(11):1222-1226, 1989. [doi]
- Design of robustly testable combinational logic circuitsSandip Kundu, Sudhakar M. Reddy, Niraj K. Jha. tcad, 10(8):1036-1048, 1991. [doi]
- On the design of robust testable CMOS combinational logic circuitsSandip Kundu, Sudhakar M. Reddy. ftcs 1988: 220-225 [doi]
- Testing for multiple faults in domino-CMOS logic circuitsNiraj K. Jha. tcad, 7(1):109-116, 1988. [doi]
- On Testable Design for CMOS Logic CircuitsJon G. Kuhl, Sudhakar M. Reddy. itc 1983: 435-445
- Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic CircuitsSudhakar M. Reddy, Madhukar K. Reddy. TC, 35(8):742-754, 1986.
- Design of Testable CMOS Logic Circuits Under Arbitrary DelaysNiraj K. Jha, Jacob A. Abraham. tcad, 4(3):264-269, 1985. [doi]