Table of Contents

• Testability Emphasis in the General Electric A/VLSI ProgramRobert C. Kroeger. 4
• Testing Trends in Automotive ElectronicsRobert F. Miller, Kenneth W. Doversberger. 5
• The Effect of the Factory of the Future on SocietyJ. A. G. Shearsmith. 6-11
• Test Pattern Compaction in VLSI TestersRobert Albrow. 12-17
• Implementing a Self-Managed Test Vector Memory with One Million ElementsSteven Ladd. 18-20
• A Suitable Test System for Gate ArrayY. Kuramitsu, Y. Gamo. 21-24
• A Tightly Coupled Multiprocessor for VLSI TestingDavid R. Emberson. 25-28
• System Architecture for Optimum DC Parameter MeasurementsJohn R. Schinabeck. 29-32
• Test Program Optimization Techniques for a High Speed Performance VLSI TesterArthur L. Downey. 33-39
• New Techniques for Manufacturing Test and Diagnosis of LSSD BoardsPeter Hansen. 40-45
• Testing Microprocessor Boards and Systems: A New ApproachJohn A. Masciola, Gary Roberts. 46-50
• FAST Technology In-Circuit Testing ConsiderationsBrian C. Crosby. 51-56
• High-Speed In-Circuit TestingSteven L. Bates. 57-63
• A New Hardware Architecture for Digital In-Circuit TestingMatt Snook, Bob Illick. 64-71
• Fixturing for Surface-Mounted DevicesRichard N. Barnes. 72-75
• Recurrent Test PatternsEdward J. McCluskey, David J. Lu. 76-82
• Testing Computer Hardware through Data Compression in Space and TimeKewal K. Saluja, Mark G. Karpovsky. 83-88
• Comparison of AC Self-Testing ProceduresZeev Barzilai, Barry K. Rosen. 89-94
• On Random Pattern Test LengthJacob Savir, Paul H. Bardell. 95-107
• Employing Massive Parallelism in Digital ATPG AlgorithmsGlenn A. Kramer. 108-114
• Test Set Reduction Using the Subscripted D-AlgorithmJ. F. McDonald, C. Benmehrez. 115-121
• Simulation Pattern Capturing System for Design Verification Using a Dynamic High Speed Functional Tester (DHSFT)David Florcik, David Low. 122-128
• Non-Stuck-At Fault Detection in nMOS Circuits by Region AnalysisMichael G. Lamoureux, Vinod K. Agarwal. 129-137
• A Practical Approach to Fault Simulation and Test Generation for Bridging FaultsMiron Abramovici, Premachandran R. Menon. 138-142
• The Sequential ATPG: A Theoretical LimitAlexander Miczo. 143-149
• Integration into the CAD EnvironmentW. Boggs. 150
• The Develpment of a Tester-Per-Pin VLSI Test System ArchitectureSteve Bisset. 151-157
• Testing Issues at the University of TexasM. Ray Mercer. 158-159
• Test Technology in the UniversityKenneth Rose. 160-161
• Incorporating Test Technology into an Undergraduate CurriculumJacob A. Abraham. 162
• Diversified TestingAl A. Tuszynski. 163-165
• Teaching TestingEdward J. McCluskey. 166-169
• Subnanosecond Timing Measurements on MOS Devices Using Modern VLSI Test SystemsMark R. Barber. 170-180
• Automatic Calibration for a VLSI Test SystemLisa Deerr. 181-187
• Individual Signal Path Calibration for Maximum Timing Accuracy in a High Pincount VLSI Test SystemMichael Catalano, Richard K. Feldman, Roberto Krutiansky, Richard Swan. 188-192
• Attainable Accuracy of Autocalibrating VLSI Test SystemsBurnell G. West. 193-199
• Optimizing the Timing Architecture of a Digital LSI Test SystemRichard F. Herlein. 200-211
• Estimating the Required Size of an Automated Test and Repair System from Subassembly Volume and Failure InformationJohn C. Howland, Pat T. Harding. 212-219
• Consideration While Introducing a Test Data Management System to the Factory FloorR. Wade Williams. 220-225
• User s Requirements for Automated Handling in Computer Manufacturing and Board TestJack H. Arabian. 226-237
• Use of In-Fab Parametric Testing for Process Control of Semiconductor ManufacturingRobert W. Atherton, David M. Campbell. 238-247
• The Role of Testing in Achieving Zero DefectsDonald S. Cleverley. 248-253
• Software Solutions Enhance ATE Networking CapabilitiesGerry Schmid. 254-259
• Self-Testing in Bit Serial VLSI Parts: High Coverage at Low CostAlan F. Murray, Peter B. Denyer, David S. Renshaw. 260-268
• A Mixed-Mode Built-In Self-Test Technique Using Scan Path and Signature AnalysisYacoub M. El-Ziq, Hamid H. Butt. 269-274
• On-Line Self-Monitoring Using Signatured Instruction StreamsMichael A. Schuette, John Paul Shen. 275-282
• An LSSD Pseudo Random Pattern Test SystemFranco Motika, John A. Waicukauski, Edward B. Eichelberger, Eric Lindbloom. 283-288
• A Digital Polarity Correlator Featuring Built-In Self Test and Self Repair MechanismsW. S. Blackley, M. A. Jack, J. R. Jordan. 289-294
• The MC6804P2 Built-In Self-TestJohn R. Kuban, Bill Bruce. 295-301
• The HITEST Test Generation System OverviewDavid J. Wharton. 302-310
• HITEST : Intelligent Test GenerationGordon D. Robinson. 311-323
• HITEST Test Generation System InterfacesColin Maunder. 324-332
• The GENESYS-Algorithm for ATPG without Fault SimulationMats Johansson. 333-337
• Computer Aided Testability Evaluation and Test GenerationChantal Robach, Ch. Malecha, G. Michel. 338-345
• A High Level Test Pattern Generation AlgorithmMasato Kawai, H. Shibano, S. Funatsu, S. Kato, T. Kurobe, K. Ookawa, T. Sasaki. 346-353
• The Impact of a VLSI Test System on the Test Throughput EquationCharles McMinn. 354-361
• A New Approach to DC Parameter Measurement in the Day of VLSITakeshi Shigematsu, Takashi Sakamoto, Yoshio Yamanaka. 362-365
• Power Supply Noise Testing of VLSI ChipsR. Y. Li, S. C. Diehl, S. Harrison. 366-370
• High-Fidelity Device Tester InterfaceShigeru Sugamori, Kunio Takeuchi, Hiromi Maruyama, Shinpei Kamata. 371-378
• New Directions for VLSI Test SystemsPhil Brothers. 379-381
• An Analysis of the Cost and Quality Impact of LSI/VLSI Technology on PCB Test StrategiesMark A. Myers. 382-395
• An Analysis of ATE Testing CostsRobert E. Huston. 396-411
• Reducing the Cost of Quality through Test Data ManagementPaul N. Manikas, Stephen G. Eichenlaub. 412-417
• Operations Management and Analysis in the Management of Electronic TestingRobert W. Atherton, Alfred H. Miller Jr., Judith E. Dayhoff. 418-427
• Total Fault Testing Using the Bipartite TransformationAndrea S. LaPaugh, Richard J. Lipton. 428-434
• On Testable Design for CMOS Logic CircuitsJon G. Kuhl, Sudhakar M. Reddy. 435-445
• Syndrome Testable Design of Combinational Networks for Detecting Stuck-At and Bridging FaultsBhargab B. Bhattacharya, Bidyut Gupta. 446-452
• Syndrome-Testable Design of Programmable Logic ArraysTeruhiko Yamada. 453-459
• Pattern Recognition of Bit Fail MapsMarc R. Faucher. 460-463
• Tester Correlation Problem in Memory Testers Used in Production LinesMasaaki Arao, Takao Tadokoro, Hiromi Maruyama, Shinpei Kamata. 464-470
• Production Test and Repair of 256K Dynamic RAMS with RedundancyDonald M. Stewart. 471-475
• Tester Independent Problem Representation and Tester Dependent Program GenerationRobert L. Hickling. 476-482
• An Adaptable Emulation Support Environment for Microprocessor SystemsGeorge F. Sprott. 483-488
• Designing the VLSI Device-to-Board Test Ukraine TranslatorL. M. Zobniw. 489-496
• An ETHERNET Based Solution to ATE NetworkingMark P. Skrzynski, Neal Shea. 497-507
• Design of High-Level Test Language for Digital LSITakuji Okamoto, Hiroyuki Shibata, Kozo Kinoshita. 508-513
• Inside a Modern Test Language CompilerDavid C. Snyder, Elaina S. Stokes, Richard C. Mahoney. 514-527
• Implementation of a Memory-Emulation Diagnostic TechniqueBrian J. Sargent. 528-531
• An Information-Rich ATE ArchitectureLarry C. Sollman. 532-537
• Structured Logic Analysis for Manufacturing TestingRobert S. Broughton. 538-545
• Logical Models of Physical FailuresC. Timoc, M. Buehler, T. Griswold, C. Pina, F. Stott, L. Hess. 546-553
• Generating Tests for Physical Failures in MOS Logic CircuitsPrithviraj Banerjee, Jacob A. Abraham. 554-559
• Testing for Timing Faults in Synchronous Sequential Integrated CircuitsYashwant K. Malaiya, Ramesh Narayanaswamy. 560-573
• Predicting Test Accuracy for Analog In-Circuit TestingMax Khazam. 574-577
• A Waveform Digitizer for Dynamic Testing of High Speed Data Conversion ComponentsJoel Halbert, Mike Koen. 578-588
• New Techniques for High Speed Analog TestingMatthew V. Mahoney. 589-597
• A General Method for Increasing Converter Accuracy and ResolutionE. A. Sloane, P. W. Dodd. 598-605
• Real-Time Automatic Calibration of Analog Test SystemsDouglas A. Blakeslee. 606-609
• A Microprocessor Based Method for Testing Transition Noise in Analog to Digital ConvertersPhil Carrier. 610-621
• Concurrent Fault Detection Using a Watchdog Processor and AssertionsAamer Mahmood, Edward J. McCluskey, David J. Lu. 622-628
• An Application of Statistical Methods for System Failure PredictionAlexander Kheruze, Ken Caruso. 629-634
• System Test Visibility Or Why Can t You Test Your ElectronicsFrederick G. Danner. 635-639
• System Test: Applications of Control Interface TestingF. Scott Davidson. 640-651
• Bayesian Models of Tests : Some Practical ResultsM. Small, D. Murray. 652-658
• Turning Test Data into InformationPat T. Harding, John C. Howland. 659-667
• A Simplified Algorithm for Testing MicroprocessorsKewal K. Saluja, Li Shen, Stephen Y. H. Su. 668-675
• Analysis of Gate Array Failures Using Functional ATEG. F. Meravi, J. J. Bell, J. C. Bernier. 676-681
• Functional Test Vector Generation for Digital LSI/VLSI DevicesTom Middleton. 682-691
• Real-Time Product Characterization by Fault Modeling and Pattern RecognitionsFeng-Hsien Warren Shih. 692-700
• Adaptive Self-Test for a MicroprocessorC. Timoc, F. Stott, K. Wickman, L. Hess. 701-705
• Design for Testability Using Logic ProgrammingPaul W. Horstmann. 706-713
• Signature Testing of Sequential MachinesSyed Zahoor Hassan. 714-718
• Testing of Bit-Serial Signal ProcessorsNick Kanopoulos, G. T. Mitchell. 719-727
• The Economics of Parallel TestingMarc A. Rich, Daniel E. Gentry. 728-737
• Parallel Testing of Non-Volatile MemoriesGarry Marks. 738-745
• Testing a High Performance Modem FilterStephen W. Bryson. 746-749
• Digital Signal Processing Test Techniques for Telecommunications Integrated CircuitsJuerg Hofer, Bob Sigsby. 750-766
• Production Testing of PCM (Digital) Audio CircuitsMark Landry. 767-770
• Chroma Voltmeter Measurement Techniques for Analog LSI DevicesRobert Craven, Joseph Schissler, Peter Konde. 771-783
• IC Quality Control by the UserRoger Dunn. 784-789
• Future of Temperature and Humidity Testing: Highly Accelerated Temperature and Humidity Stress Test (HAST)Sushil K. Malik, Jeffrey E. Gunn, Robert E. Camenga. 790-795
• A Convenient Algebra of Quality for Interpreting ATE Test DataKemon P. Taschioglou. 796-803
• Safe Operating Zones for Digital In-Circuit TestingG. Siva Bushanam, H. Story. 804