The following publications are possibly variants of this publication:
- Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test TechniqueAsma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herve Naudet. tcas, 62-I(10):2391-2400, 2015. [doi]
- Reduced-Code Linearity Testing of Pipeline ADCsAsma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herve Naudet, Gerard Bret. dt, 30(6):80-88, 2013. [doi]
- Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCsGuillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragan, Salvador Mir. vts 2017: 1-6 [doi]
- Reduced code linearity testing of pipeline adcs in the presence of noiseAsma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herve Naudet, Gerard Bret. vts 2013: 1-6 [doi]
- A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCsGuillaume Renaud, Manuel J. Barragan, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet. et, 32(4):407-421, 2016. [doi]
- Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCsRenato S. Feitoza, Manuel J. Barragan, Salvador Mir. vlsi 2019: 263-268 [doi]