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Won Young Lee, Lee-Sup Kim. A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation. IEEE Trans. on Circuits and Systems, 59-I(11):2518-2528, 2012. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A 5.4 Gb/s clock and data recovery circuit using the seamless loop transition scheme without phase noise degradationWon Young Lee, Lee-Sup Kim. iscas 2011: 430-433 [doi] A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase ResolutionChang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. ieicet, 90-C(1):165-170, 2007. [doi] A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolutionChang-Kyung Seong, Seung Woo Lee, Woo-Young Choi. iscas 2006: [doi]
The following publications are possibly variants of this publication: