The following publications are possibly variants of this publication:
- A 100Gb/s quad-rate transformer-coupled injection-locking CDR circuit in 65nm CMOSFanta Chen, Jen-Ming Wu, Jenny Yi-Chun Liu, Mau-Chung Frank Chang. iscas 2013: 1950-1953 [doi]
- A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOSShijie Hu, Chen Jia, Ke Huang, Chun Zhang, Xuqiang Zheng, Zhihua Wang. iscas 2012: 309-312 [doi]
- A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOSYang You, Sudipto Chakraborty, Rui Wang, Jinghong Chen. asscc 2015: 1-4 [doi]
- Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOSKangmin Hu, Tao Jiang, Samuel Palermo, Patrick Yin Chiang. cicc 2011: 1-4 [doi]