The following publications are possibly variants of this publication:
- Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAsYu-Chen Chen, Sheng-Yen Chen, Yao-Wen Chang. iccad 2014: 647-654 [doi]
- RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAsChak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka Chun Lam, Jian Kuang 0001, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu. iccad 2016: 67 [doi]
- UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packingWuxi Li, Shounak Dhar, David Z. Pan. iccad 2016: 66 [doi]
- UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware PackingWuxi Li, Shounak Dhar, David Z. Pan. tcad, 37(4):869-882, 2018. [doi]
- RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAsGengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka Chun Lam, Jian Kuang 0001, Evangeline F. Y. Young, Bei Yu 0001. tcad, 37(10):2022-2035, 2018. [doi]
- Layout driven FPGA packing algorithm for performance optimizationLinfeng Mo, Chang Wu, Lei He, Gengsheng Chen. ieiceee, 14(11):20170419, 2017. [doi]