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Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara. A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. In ICCD. pages 202-205, 1993.
Possibly Related PublicationsThe following publications are possibly variants of this publication: An 8.8-ns 54×54-bit multiplier with high speed redundant binary architectureHiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko. jssc, 31(6):773-783, 1996. [doi]
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