The following publications are possibly variants of this publication:
- Automatic gate-level synthesis of speed-independent circuitsPeter A. Beerel, Teresa H. Y. Meng. iccad 1992: 581-586 [doi]
- POSET timing and its application to the synthesis and verification of gate-level timed circuitsChris J. Myers, Tomas Rokicki, Teresa H. Y. Meng. tcad, 18(6):769-786, 1999. [doi]
- Direct synthesis of timed circuits from free-choice STGsSung Tae Jung, Chris J. Myers. tcad, 21(3):275-290, 2002. [doi]
- High Level Synthesis of Timed Asynchronous CircuitsTomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers. async 2005: 178-189 [doi]
- Automatic synthesis of asynchronous circuits from high-level specificationsTeresa H. Y. Meng, Robert W. Brodersen, David G. Messerschmitt. tcad, 8(11):1185-1205, 1989. [doi]