Kenji Noda, Koichi Takeda 0001, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi. An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. J. Solid-State Circuits, 36(3):510-515, 2001. [doi]
@article{NodaTMIMKIANITH01,
title = {An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield},
author = {Kenji Noda and Koichi Takeda 0001 and Koujirou Matsui and Shinya Ito and Sadaaki Masuoka and Hideaki Kawamoto and Nobuyuki Ikezawa and Yoshiharu Aimoto and Noritsugu Nakamura and Takahiro Iwasaki and Hideo Toyoshima and Tadahiko Horiuchi},
year = {2001},
doi = {10.1109/4.910490},
url = {https://doi.org/10.1109/4.910490},
researchr = {https://researchr.org/publication/NodaTMIMKIANITH01},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {36},
number = {3},
pages = {510-515},
}