The following publications are possibly variants of this publication:
- Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICsBrandon Noia. PhD thesis, Duke University, Durham, NC, USA, 2014. [doi]
- Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICsBrandon Noia, Krishnendu Chakrabarty. Springer, 2014. [doi]
- A structured and scalable test access architecture for TSV-based 3D stacked ICsErik Jan Marinissen, Jouke Verbree, Mario H. Konijnenburg. vts 2010: 269-274 [doi]
- Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICsBrandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree. tcad, 30(11):1705-1718, 2011. [doi]
- Testing TSV-based three-dimensional stacked ICsErik Jan Marinissen. date 2010: 1689-1694 [doi]
- Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICsYoung-Joon Lee, Rohan Goel, Sung Kyu Lim. iccad 2009: 645-651 [doi]
- Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICsSergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen. itc 2013: 1-10 [doi]
- Challenges in testing TSV-based 3D stacked ICs: Test flows, test contents, and test accessErik Jan Marinissen. apccas 2010: 544-547 [doi]