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Kaoru Okazaki, Toshihiko Yahara. Efficient Logic Verification and Test Validation for MOS LSI Circuits. In Proceedings International Test Conference 1981, Philadelphia, PA, USA, October 1981. pages 530-535, IEEE Computer Society, 1981.
Possibly Related PublicationsThe following publications are possibly variants of this publication: Delay-Time Modeling for ED MOS Logic LSITakeshi Tokuda, Kaoru Okazaki, K. Sakashita, I. Ohkura, T. Enomoto. tcad, 2(3):129-134, 1983. [doi]
The following publications are possibly variants of this publication: