Clock Gating Synthesis of Pulsed-Latch Circuits - researchr publication related

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Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin. Clock Gating Synthesis of Pulsed-Latch Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 31(7):1019-1030, 2012. [doi]

The following publications are possibly variants of this publication:

Pulser gating: A clock gating of pulsed-latch circuitsSangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin. aspdac 2011: 190-195 [doi]

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking powerSeungwhun Paik, Gi-Joon Nam, Youngsoo Shin. iccad 2011: 640-646 [doi]

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuitsHyein Lee, Seungwhun Paik, Youngsoo Shin. iccad 2008: 224-229 [doi]

Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed LatchesHyein Lee, Seungwhun Paik, Youngsoo Shin. tcad, 29(3):355-366, 2010. [doi]

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree OptimizationSangmin Kim, Seokhyeong Kang, Youngsoo Shin. todaes, 21(3):51, 2016. [doi]

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