A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO - researchr publication

researchr

You are not signed in
Sign in
Sign up

Chengxian Pan, Chunqi Shi, Guoliang Zhao, Boxiao Liu, Leilei Huang, Runxi Zhang. A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO. IEICE Electronic Express, 19(24):20220432, 2022. [doi]

Abstract is missing.

runs on WebDSL