3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections - researchr publication authors

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Katsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, Steven L. Wright, Bing Dang, Chirag S. Patel, Bucknell C. Webb, J. Maria, Edmund J. Sprogis, S. K. Kang, Robert J. Polastre, Raymond R. Horton, John U. Knickerbocker. 3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. IBM Journal of Research and Development, 52(6):611-622, 2008. [doi]

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