Katsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, Steven L. Wright, Bing Dang, Chirag S. Patel, Bucknell C. Webb, J. Maria, Edmund J. Sprogis, S. K. Kang, Robert J. Polastre, Raymond R. Horton, John U. Knickerbocker. 3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. IBM Journal of Research and Development, 52(6):611-622, 2008. [doi]
@article{SakumaATWDPWMSKPHK08,
title = {3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections},
author = {Katsuyuki Sakuma and Paul S. Andry and Cornelia K. Tsang and Steven L. Wright and Bing Dang and Chirag S. Patel and Bucknell C. Webb and J. Maria and Edmund J. Sprogis and S. K. Kang and Robert J. Polastre and Raymond R. Horton and John U. Knickerbocker},
year = {2008},
doi = {10.1147/JRD.2008.5388567},
url = {http://dx.doi.org/10.1147/JRD.2008.5388567},
tags = {C++},
researchr = {https://researchr.org/publication/SakumaATWDPWMSKPHK08},
cites = {0},
citedby = {0},
journal = {IBM Journal of Research and Development},
volume = {52},
number = {6},
pages = {611-622},
}