Zero Cost Test Point Insertion Technique for Structured ASICs - researchr publication related

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Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell. Zero Cost Test Point Insertion Technique for Structured ASICs. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 357-363, IEEE Computer Society, 2007. [doi]

The following publications are possibly variants of this publication:

Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICsRajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell. ats 2006: 339-348 [doi]

A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan DesignsSeongmoon Wang, Srimat T. Chakradhar. itc 2003: 574-583 [doi]

A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designsSeongmoon Wang, Srimat T. Chakradhar. tcad, 25(8):1555-1564, 2006. [doi]

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