The following publications are possibly variants of this publication:
- 4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XORNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. vlsi 2010: 364-368 [doi]
- LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplierNazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine. mj, 43(4):244-249, 2012. [doi]
- 2PADCL: Two Phase drive Adiabatic Dynamic CMOS LogicYasuhiro Takahashi, Youhei Fukuta, Toshikazu Sekine, Michio Yokoyama. apccas 2006: 1484-1487 [doi]
- A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logicKazunari Kato, Yasuhiro Takahashi, Toshikazu Sekine. newcas 2015: 1-4 [doi]
- 4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOSNazrul Anuar, Yasuhiro Takahashi, Toshikazu Sekine. ecctd 2009: 65-68 [doi]