The following publications are possibly variants of this publication:
- The New BCD Subtractor and Its Reversible Logic ImplementationHimanshu Thapliyal, M. B. Srinivas. APCSAC 2006: 466-472 [doi]
- Design of Novel Reversible Carry Look-Ahead BCD SubtractorHimanshu Thapliyal, Sumedha K. Gupta. IEEEcit 2006: 253-258 [doi]
- Design of efficient reversible logic-based binary and BCD adder circuitsHimanshu Thapliyal, Nagarajan Ranganathan. jetc, 9(3):17, 2013. [doi]
- Design of Efficient Reversible Binary Subtractors Based on a New Reversible GateHimanshu Thapliyal, Nagarajan Ranganathan. isvlsi 2009: 229-234 [doi]
- Reversible Logic Synthesis of Half, Full and Parallel SubtractorsHimanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia. csreaESA 2005: 165-181
- Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r FormatHimanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas. vlsid 2006: 387-392 [doi]
- Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic ImplementationHimanshu Thapliyal, Hamid R. Arabnia. cdes 2006: 64-69
- A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-SubtractorHimanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia. csreaESA 2005: 60-68
- A new reversible design of BCD adderHimanshu Thapliyal, N. Ranganathan. date 2011: 1180-1183 [doi]