The following publications are possibly variants of this publication:
- A Family of Parallel-Pre.x Modulo 2n - 1 AddersGiorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou. asap 2003: 326-336 [doi]
- New architectures for modulo 2N - 1 addersGiorgos Dimitrakopoulos, D. G. Nikolos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou. icecsys 2005: 1-4 [doi]
- Modulo 2n±1 Adder Design Using Select-Prefix BlocksCostas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos. TC, 52(11):1399-1406, 2003. [doi]
- A Family of Area-Time Efficient Modulo 2n+1 AddersHaridimos T. Vergos. isvlsi 2010: 442-443 [doi]
- On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic ComponentsHaridimos T. Vergos, Dimitris Bakalis. dsd 2008: 752-759 [doi]