The following publications are possibly variants of this publication:
- A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST ArchitectureIoannis Voyiatzis, Costas Efstathiou, H. Antonopoulou. ets 2011: 206 [doi]
- Input Vector Monitoring Concurrent BIST Architecture Using SRAM CellsIoannis Voyiatzis, Costas Efstathiou. tvlsi, 22(7):1625-1629, 2014. [doi]
- Input vector monitoring on line concurrent BIST based on multilevel decoding logicIoannis Voyiatzis. date 2012: 1251-1256 [doi]
- An Input Vector Monitoring Concurrent BIST scheme exploiting Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis. iolts 2009: 206-207 [doi]
- R-CBIST: an effective RAM-based input vector monitoring concurrent BIST techniqueIoannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis. itc 1998: 918-925 [doi]
- A low-cost input vector monitoring concurrent BIST schemeIoannis Voyiatzis, Costas Efstathiou, Cleo Sgouropoulou. iolts 2013: 179-180 [doi]