The following publications are possibly variants of this publication:
- A built-in test circuit for open defects at interconnects between dies in 3D ICsWidianto, Hiroyuki Yotsuyanagi, Akira Ono, Masao Takagi, Masaki Hashizume. 3dic 2012: 1-5 [doi]
- A built-in supply current test circuit for electrical interconnect tests of 3D ICsMasaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. 3dic 2014: 1-6 [doi]
- Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICsMasaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu. ats 2013: 13-18 [doi]