A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur - researchr publication related

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Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun 0001, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang 0092, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada 0001. A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur. J. Solid-State Circuits, 60(6):2106-2121, June 2025. [doi]

The following publications are possibly variants of this publication:

10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated JitterDingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada. isscc 2024: 192-194 [doi]

A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional SpursDihang Yang, Asad A. Abidi, Hooman Darabi, Hao Xu, David Murphy, Hao Wu 0005, Zhaowen Wang. isscc 2019: 266-268 [doi]

Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider ControllersXu Wang, Michael Peter Kennedy. icecsys 2023: 1-5 [doi]

29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional SpurQiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen. isscc 2021: 410-412 [doi]

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