Abstract is missing.
- ChaoPIM: A PIM-based Protection Framework for DNN Accelerators Using Chaotic EncryptionNing Lin, Xiaoming Chen 0003, Chunwei Xia, Jing Ye, Xiaowei Li. 1-6 [doi]
- Twine Stack: A Hybrid Mechanism Achieving Less Cost for Return Address ProtectionQizhen Xu, Liwei Chen, Gang Shi. 7-12 [doi]
- Lightweight Hardware-Based Memory Protection Mechanism on IoT ProcessorsHung-Yao Chi, Kuen-Jong Lee, Tzu-Chun Jao. 13-18 [doi]
- Application of Residue Sampling to RF/AMS Device TestingShogo Katayama, Yudai Abe, Anna Kuwana, Koji Asami, Masahiro Ishida, Ryuya Ohta, Haruo Kobayashi 0001. 19-24 [doi]
- Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural NetworkMichihiro Shintani, Mamoru Ishizaka, Michiko Inoue. 25-30 [doi]
- Temperature-Aware Evaluation and Mitigation of Logic Soft Errors Under Circuit VariationsWarin Sootkaneung, Sasithorn Chookaew, Suppachai Howimanporn. 31-36 [doi]
- Note on CapsNet-Based Wafer Map Defect Pattern ClassificationItsuki Fujita, Yoshikazu Nagamura, Masayuki Arai, Satoshi Fukumoto. 37-42 [doi]
- SeGa: A Trojan Detection Method Combined With Gate SemanticsYunying Ye, Shan Li, Haihua Shen, Huawei Li, Xiaowei Li 0001. 43-48 [doi]
- CausalTester: Measuring the Consistency of Replicated Services via Causality SemanticsYu Tang, Le Zhao, Wei Yuan, Xu Wang 0007. 49-54 [doi]
- Detection of Stuck-at and Bridging Fault in Reversible Circuits using an Augmented CircuitMousum Handique, Jantindra Kumar Deka, Santosh Biswas. 55-60 [doi]
- Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data MiningArne Grünhagen, Julien Branlard, Annika Eichler, Gianluca Martino, Görschwin Fey, Marina Tropmann-Frick. 61-66 [doi]
- A Novel Compaction Approach for SBST Test ProgramsJuan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 67-72 [doi]
- Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined ProcessorNikolaos Ioannis Deligiannis, Riccardo Cantoro, Tobias Faller, Tobias Paxian, Bernd Becker 0001, Matteo Sonza Reorda. 73-78 [doi]
- Side-Channel Attacks on Triple Modular Redundancy SchemesFelipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini. 79-84 [doi]
- Polynomial Formal Verification of Prefix AddersAlireza Mahzoon, Rolf Drechsler. 85-90 [doi]
- Further Analysis of Laser-induced IR-dropWilliam Souza da Cruz, Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Jean-Baptiste Rigaud, Guillaume Hubert. 91-96 [doi]
- Investigation of 0.18μm CMOS Sensitivity to BTI and HCI Mechanisms under Extreme Thermal Stress ConditionsYen Tran, Toshihiro Nomura, Mohamed Salim Cherchali, Claire Tassin, Yann Deval, Cristell Maneux. 97-102 [doi]
- On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern GenerationXijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz. 103-108 [doi]
- Positive and Negative Extra Clocking of LFSR Seeds for Reduced Numbers of Stored TestsIrith Pomeranz. 109-114 [doi]
- Towards a Secure Integrated Heterogeneous Platform via Cooperative CPU/GPU EncryptionZhendong Wang, Rujia Wang, Zihang Jiang, Xulong Tang, Shouyi Yin, Yang Hu 0001. 115-120 [doi]
- A Design of Approximate Voting Schemes for Fail-Operational SystemsHideyuki Ichihara, Kazunori Yukihiro, Tomoo Inoue. 121-126 [doi]
- GPU-Accelerated Timing Simulation of Systolic-Array-Based AI AcceleratorsStefan Holst, Lim Bumun, Xiaoqing Wen. 127-132 [doi]
- Analyzing Transient Faults and Functional Error Rates of a RISC-V Core: A Case StudyDun-An Yang, Jing-Jia Liou, Harry H. Chen. 133-138 [doi]
- High Precision Measurement of Sub-Nano Ampere Current in ATE EnvironmentKeno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Gaku Ogihara, Daisuke Iimori, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi 0001. 139-140 [doi]
- A Power Reduction Method for Scan Testing in Ultra-Low Power DesignsHiroyuki Iwata, Yoichi Maeda, Jun Matsushima. 141 [doi]