Table of Contents

• Preventing Scan Attack through Test Response EncryptionSatyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh. 1-6 [doi]
• A State Assignment Method to Improve Transition Fault Coverage for ControllersMasayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa. 1-4 [doi]
• A Low Capture Power Oriented X-filling Method Using Partial MaxSAT IterativelyToshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, Masavuki Arai. 1-6 [doi]
• A Comprehensive Evaluation of the Effects of Input Data on the Resilience of GPU ApplicationsFritz G. Previlon, Charu Kalra, David R. Kaeli, Paolo Rech. 1-6 [doi]
• Understanding of GPU Architectural Vulnerability for Deep Learning WorkloadsDanny Santoso, Hyeran Jeon. 1-6 [doi]
• Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAsZhen Gao, Jinhua Zhu, Lina Yan, Tong Yan, Pedro Reviriego. 1-4 [doi]
• Scalable and Configurable Multi-Chip SRAM in a Package for Space ApplicationsAleksandar Simevski, Patryk Skoncej, Cristiano Calligaro, Milos Krstic. 1-6 [doi]
• Increasing the Efficiency and Efficacy of Selective-Hardening for Parallel ApplicationsDaniel Oliveira, Philippe O. A. Navaux, Paolo Rech. 1-6 [doi]
• Effects of Heavy Ion and Proton Irradiation on a SLC NAND Flash MemoryLucas Matana Luza, Alexandre Besser, Viyas Gupta, Arto Javanainen, Ali Mohammadzadeh, Luigi Dilillo. 1-6 [doi]
• Protecting Large Word Size Memories against MCUs with 3-bit Burst Error CorrectionJiaqiang Li, Pedro Reviriego, Liyi Xiao, Alexander Klockmann. 1-4 [doi]
• Analog Test Interface for IEEE 1687 Employing Split SAR Architecture to Support Embedded Instrument Dependability ApplicationsJerrin Pathrose, Leon van de Logt, Hans G. Kerkhoff. 1-4 [doi]
• Efficient Error-Tolerant Quantized Neural Network AcceleratorsGiulio Gambardella, Johannes Kappauf, Michaela Blott, Christoph Doehring, Martin Kumm, Peter Zipf, Kees A. Vissers. 1-6 [doi]
• Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor ProcessingMarkus Ulbricht, Rizwan Tariq Syed, Milos Krstic. 1-4 [doi]
• Testing of In-Memory-Computing 8T SRAMsTsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun. 1-4 [doi]
• State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State MachinesHideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue. 1-6 [doi]
• Predicting Single Event Effects in DRAMDonald Kline Jr., Stephen Longofono, Rami G. Melhem, Alex K. Jones. 1-6 [doi]
• Simulating Wear-out Effects of Asymmetric Multicores at the Architecture LevelNikos Foutris, Christos Kotselidis, Mikel Luján. 1-6 [doi]
• Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration MemoryMahsa Mousavi, Hamid Reza Pourshaghaghi, Henk Corporaal, Akash Kumar 0001. 1-6 [doi]
• On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGABoyang Du, Sarah Azimi, Corrado De Sio, Ludovica Bozzoli, Luca Sterpone. 1-6 [doi]
• On the Criticality of Caches in Fault-Tolerant Processors for SpaceStefano Di Mascio, Alessandra Menicucci, Eberhard Gill, Gianluca Furano, Claudio Monteleone. 1-4 [doi]
• Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel CellsShanshan Liu, Pedro Reviriego, Kazuteru Namba, Salvatore Pontarelli, Livi Xiao, Fabrizio Lombardi. 1-4 [doi]
• Evaluation of TMR effectiveness for soft error mitigation in SHyLoC compression IP core implemented on Zynq SoC under heavy ion radiationAntonio Sánchez, Yubal Barrios, Lucana Santos, Roberto Sarmiento. 1-4 [doi]
• A Fault-Tolerant MPSoC For CubeSatsChristian M. Fuchs, Pai Chou, Xiaoqing Wen, Nadia M. Murillo, Gianluca Furano, Stefan Holst, Antonis Tavoularis, Shyue-Kung Lu, Aske Plaat, Kostas Marinis. 1-6 [doi]
• CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in MulticoreAvishek Choudhury, Biplab K. Sikdar. 1-4 [doi]
• Detecting SEUs in Noisy Digital Imagers with small pixelsGlenn H. Chapman, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Bifei Huang, Hao Yang, Israel Koren, Zahava Koren. 1-6 [doi]
• On-line Testing for Autonomous Systems driven by RISC-V Processor Design VerificationAnnachiara Ruospo, Riccardo Cantoro, Ernesto Sánchez 0001, Pasquale Davide Schiavone, Angelo Garofalo, Luca Benini. 1-6 [doi]
• Challenges of Reliability Assessment and Enhancement in Autonomous SystemsMaksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu. 1-6 [doi]
• High Performance Memory RepairFeroze Merchant, Anandraj Devarajan, Anik Basu, David Ashen, Brandon Yelton, Prashant D. Joshi. 1-4 [doi]
• Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue CheckingAna Lasheras, Ramon Canal, Eva Rodríguez, Luca Cassano. 1-6 [doi]
• Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor SensingLuca Gnoli, Giuseppe Carnicelli, Alessio Parisi, Luca Urbinati, Burim Kabashi, Fabio Michieletti, Sebastian Ignacio Peradotto Ibarra, Marco Vacca, Mariagrazia Graziano, Jimson Mathew, Marco Ottavi. 1-4 [doi]
• Parity-Based Concurrent Error Detection Schemes for the ChaCha Stream CipherAlexander Zeh, Manuela Meier, Viola Rieger. 1-4 [doi]
• Rebooting Computing: The Challenges for Test and ReliabilityAlberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Elena I. Vatajelu, Giorgio Di Natale, Lorena Anghel, S. Nagarajan, Moritz Fieback, Said Hamdioui. 8138-8143 [doi]
• Combining Cluster Sampling and ACE analysis to improve fault-injection based reliability evaluation of GPU-based systemsAlessandro Vallero, Stefano Di Carlo. 8138-8143 [doi]